`SourceExcitation`#

class pyedb.grpc.database.source_excitations.SourceExcitation(pedb)#

Bases: SourceExcitationInternal

Manage sources and excitations.

Examples

>>> # Initialize EDB session
>>> from pyedb import Edb
>>> edb = Edb(edbpath="path/to/your/edb")

>>> # Access SourceExcitation class
>>> source_excitations = edb.source_excitation

>>> # 1. create_source_on_component
>>> # Create voltage source on component pins
>>> from pyedb.grpc.database.utility.sources import Source, SourceType
>>> source = Source(
...     source_type=SourceType.Vsource,
...     name="V1",
...     positive_node=("U1", "VCC"),
...     negative_node=("U1", "GND"),
...     amplitude="1V",
...     phase="0deg",
...     impedance="50ohm",
... )
>>> source_excitations.create_source_on_component([source])

>>> # 2. create_port
>>> # Create port between two terminals
>>> pos_terminal = edb.terminals["MyTerminal"]
>>> ref_terminal = edb.terminals["MyRefTerminal"]
>>> port = source_excitations.create_port(pos_terminal, ref_terminal)

>>> # 3. create_port_on_pins
>>> # Create circuit port between component pins
>>> port_term = source_excitations.create_port_on_pins(
...     refdes="U1", pins="Pin1", reference_pins=["GND_Pin1", "GND_Pin2"], impedance=50, port_name="Port1"
... )

>>> # 4. create_port_on_component
>>> # Create coaxial ports on component nets
>>> source_excitations.create_port_on_component(
...     component="U1", net_list=["PCIe_RX0", "PCIe_RX1"], port_type=SourceType.CoaxPort, reference_net="GND"
... )

>>> # 5. add_port_on_rlc_component
>>> # Replace RLC component with circuit port
>>> source_excitations.add_port_on_rlc_component("R1")

>>> # 6. _create_terminal (Internal method - typically not called directly)

>>> # 7. _create_pin_group_terminal (Internal method)

>>> # 8. create_coax_port
>>> # Create coaxial port on padstack
>>> pin = edb.components["U1"].pins["Pin1"]
>>> port_name = source_excitations.create_coax_port(pin)

>>> # 9. create_circuit_port_on_pin
>>> # Create circuit port between two pins
>>> pin1 = edb.components["U1"].pins["Pin1"]
>>> pin2 = edb.components["U1"].pins["Pin2"]
>>> port_name = source_excitations.create_circuit_port_on_pin(pin1, pin2, 50, "Port1")

>>> # 10. create_voltage_source_on_pin
>>> # Create voltage source between pins
>>> source_name = source_excitations.create_voltage_source_on_pin(pin1, pin2, 3.3, 0, "V1")

>>> # 11. create_current_source_on_pin
>>> # Create current source between pins
>>> source_name = source_excitations.create_current_source_on_pin(pin1, pin2, 0.1, 0, "I1")

>>> # 12. create_resistor_on_pin
>>> # Create resistor between pins
>>> res_name = source_excitations.create_resistor_on_pin(pin1, pin2, 100, "R1")

>>> # 13. create_circuit_port_on_net
>>> # Create port between component nets
>>> port_name = source_excitations.create_circuit_port_on_net(
>>> "U1", "SignalNet", "U1", "GND", 50, "Port1"
>>> )

>>> # 14. create_voltage_source_on_net
>>> # Create voltage source between nets
>>> source_name = source_excitations.create_voltage_source_on_net(
>>> "U1", "VCC", "U1", "GND", 5.0, 0, "VCC_Source"
>>> )

>>> # 15. create_current_source_on_net
>>> # Create current source between nets
>>> source_name = source_excitations.create_current_source_on_net(
>>> "U1", "InputNet", "U1", "GND", 0.02, 0, "InputCurrent"
>>> )

>>> # 16. create_coax_port_on_component
>>> # Create coaxial ports on component
>>> ports = source_excitations.create_coax_port_on_component(
...     ["U1", "U2"], ["PCIe_RX0", "PCIe_TX0"], delete_existing_terminal=True
... )

>>> # 17. create_differential_wave_port
>>> # Create differential wave port
>>> pos_prim = edb.modeler.primitives[0]
>>> neg_prim = edb.modeler.primitives[1]
>>> port_name, diff_port = source_excitations.create_differential_wave_port(
...     pos_prim.id, [0, 0], neg_prim.id, [0, 0.2], "DiffPort"
... )

>>> # 18. create_wave_port
>>> # Create wave port
>>> port_name, wave_port = source_excitations.create_wave_port(pos_prim.id, [0, 0], "WavePort")

>>> # 19. create_bundle_wave_port
>>> # Create bundle wave port
>>> port_name, bundle_port = source_excitations.create_bundle_wave_port(
...     [pos_prim.id, neg_prim.id], [[0, 0], [0, 0.2]], "BundlePort"
... )

>>> # 20. create_dc_terminal
>>> # Create DC terminal
>>> source_excitations.create_dc_terminal("U1", "VCC", "VCC_Terminal")

>>> # 21. create_voltage_probe
>>> # Create voltage probe
>>> probe = source_excitations.create_voltage_probe(term1, term2)

>>> # 22. place_voltage_probe
>>> # Place voltage probe between points
>>> source_excitations.place_voltage_probe(
...     "Probe1", "SignalNet", [0, 0], "TopLayer", "GND", [0.1, 0.1], "BottomLayer"
... )

>>> # Save and close EDB
>>> edb.save()
>>> edb.close()

Overview#

Methods

`create_source_on_component`	Create voltage, current source, or resistor on component.
`create_port`	Create a port.
`create_port_on_pins`	Create circuit port between pins and reference ones.
`create_port_on_component`	Create ports on a component.
`add_port_on_rlc_component`	Deactivate RLC component and replace it with a circuit port.
`add_rlc_boundary`	Add RLC gap boundary on component and replace it with a circuit port.
`create_coax_port`	Create HFSS 3Dlayout coaxial lumped port on a pastack
`create_circuit_port_on_pin`	Create a circuit port on a pin.
`create_voltage_source_on_pin`	Create a voltage source.
`create_current_source_on_pin`	Create a voltage source.
`create_resistor_on_pin`	Create a Resistor boundary between two given pins..
`create_circuit_port_on_net`	Create a circuit port on a NET.
`create_voltage_source_on_net`	Create a voltage source.
`create_current_source_on_net`	Create a voltage source.
`create_coax_port_on_component`	Create a coaxial port on a component or component list on a net or net list.
`check_before_terminal_assignement`
`create_differential_wave_port`	Create a differential wave port.
`create_horizontal_wave_port`	Create a horizontal wave port around one or more vias inside a void.
`create_wave_port`	Create a wave port.
`create_edge_port_vertical`	Create a vertical edge port.
`create_edge_port_horizontal`	Create a horizontal edge port.
`create_lumped_port_on_net`	Create an edge port on nets. This command looks for traces and polygons on the
`create_vertical_circuit_port_on_clipped_traces`	Create an edge port on clipped signal traces.
`create_bundle_wave_port`	Create a bundle wave port.
`create_hfss_ports_on_padstack`	Create an HFSS port on a padstack.
`get_ports_number`	Return the total number of excitation ports in a layout.
`get_point_terminal`	Place terminal between two points.
`create_rlc_boundary_on_pins`	Create hfss rlc boundary on pins.
`get_edge_from_port`
`create_edge_port`
`create_edge_port_on_polygon`	Create lumped port between two edges from two different polygons. Can also create a vertical port when
`create_port_between_pin_and_layer`	Create circuit port between pin and a reference layer.
`create_current_source`	Create a current source.
`create_current_source_on_pin_group`	Create current source between two pin groups.
`create_voltage_source`	Create a voltage source.
`create_voltage_source_on_pin_group`	Create voltage source between two pin groups.
`create_voltage_probe`	Create a voltage probe.
`create_voltage_probe_on_pin_group`	Create voltage probe between two pin groups.
`create_dc_terminal`	Create a dc terminal.
`create_circuit_port_on_pin_group`	Create a port between two pin groups.
`place_voltage_probe`	Place a voltage probe between two points.
`create_padstack_instance_terminal`
`create_point_terminal`
`create_edge_terminal`
`create_bundle_terminal`
`create_pin_group_terminal`
`create_terminal_from_pin_group`

Properties

`pin_groups`	All layout pin groups.
`excitations`	Get all ports.
`ports`	Get all ports.
`sources`	Get all sources.
`probes`	Get all probes.

Import detail#

from pyedb.grpc.database.source_excitations import SourceExcitation

Property detail#

property SourceExcitation.pin_groups: Dict[str, Any]#

All layout pin groups.

Returns:

dict: Dictionary of pin groups with names as keys and pin group objects as values.

Examples

>>> from pyedb import Edb
>>> edbapp = Edb("myaedbfolder", edbversion="2021.2")
>>> pin_groups = edbapp.siwave.pin_groups
>>> for name, group in pin_groups.items():
...     print(f"Pin group {name} has {len(group.pins)} pins")

property SourceExcitation.excitations: Dict[str, pyedb.grpc.database.ports.ports.BundleWavePort | pyedb.grpc.database.ports.ports.GapPort | pyedb.grpc.database.ports.ports.CircuitPort | pyedb.grpc.database.ports.ports.CoaxPort | pyedb.grpc.database.ports.ports.WavePort]#

Get all ports.

Deprecated since version 0.70.0: Use :attr: ports instead.

Returns:

port dictionaryDict[str, [pyedb.grpc.database.ports.ports.ports.GapPort,: pyedb.grpc.database.ports.ports.ports.WavePort, pyedb.grpc.database.ports.ports.CircuitPort, pyedb.grpc.database.ports.ports.CoaxPort, pyedb.grpc.database.ports.ports.BundleWavePort]]

property SourceExcitation.ports: Dict[str, pyedb.grpc.database.ports.ports.BundleWavePort | pyedb.grpc.database.ports.ports.GapPort | pyedb.grpc.database.ports.ports.CircuitPort | pyedb.grpc.database.ports.ports.CoaxPort | pyedb.grpc.database.ports.ports.WavePort]#

Get all ports.

Returns:

port dictionaryDict[str, [pyedb.grpc.database.ports.ports.ports.GapPort,: pyedb.grpc.database.ports.ports.ports.WavePort, pyedb.grpc.database.ports.ports.CircuitPort, pyedb.grpc.database.ports.ports.CoaxPort, pyedb.grpc.database.ports.ports.BundleWavePort]]

property SourceExcitation.sources: Dict[str, Any]#: Get all sources.

property SourceExcitation.probes: Dict[str, Any]#: Get all probes.

Method detail#

SourceExcitation.create_source_on_component(sources: pyedb.grpc.database.utility.sources.Source | List[pyedb.grpc.database.utility.sources.Source] | None = None) → bool#

Create voltage, current source, or resistor on component.

Parameters:

sourceslist[Source]: List of pyedb.grpc.utility.sources.Source objects.

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> from pyedb.grpc.database.utility.sources import Source, SourceType
>>> edb = Edb()
>>> source = Source(source_type=SourceType.Vsource, amplitude="1V", ...)
>>> edb.excitation_manager.create_source_on_component([source])

SourceExcitation.create_port(terminal: pyedb.grpc.database.terminal.terminal.Terminal, ref_terminal: pyedb.grpc.database.terminal.terminal.Terminal | None = None, is_circuit_port: bool = False, name: str | None = None) → Any#

Create a port.

Parameters:

terminalclass:pyedb.dotnet.database.edb_data.terminals.EdgeTerminal,: class:pyedb.grpc.database.terminals.PadstackInstanceTerminal, class:pyedb.grpc.database.terminals.PointTerminal, class:pyedb.grpc.database.terminals.PinGroupTerminal, Positive terminal of the port.
ref_terminalclass:pyedb.grpc.database.terminals.EdgeTerminal,: class:pyedb.grpc.database.terminals.PadstackInstanceTerminal, class:pyedb.grpc.database.terminals.PointTerminal, class:pyedb.grpc.database.terminals.PinGroupTerminal, optional Negative terminal of the port.
is_circuit_portbool, optional: Whether it is a circuit port. The default is False.
name: str, optional: Name of the created port. The default is None, a random name is generated.
Returns
——-
:class:`GapPort ` or
:class:`WavePort `: Created port object.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> term = edb.terminals["MyTerminal"]
>>> ref_term = edb.terminals["RefTerminal"]
>>> port = edb.excitation_manager.create_port(term, ref_term, name="Port1")

SourceExcitation.create_port_on_pins(refdes: str | pyedb.grpc.database.components.Component, pins: int | str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance | List[int | str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], reference_pins: int | str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance | List[int | str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance] = None, impedance: str | float = '50ohm', port_name: str | None = None, pec_boundary: bool = False, pingroup_on_single_pin: bool = False) → pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal#

Create circuit port between pins and reference ones.

Parameters:

refdesstr or Component: Component reference designator or Component object.
pinsint, str, PadstackInstance, or list: Pin specifier(s) or instance(s) where the port terminal is to be created. A single pin name or a list of several can be provided. If several pins are provided, a pin group is created. Pin specifiers can be the global EDB object ID, padstack instance name, or pin name on the component with refdes. For example, for pin Pin1 on component U1: "U1-Pin1", "Pin1" with refdes="U1", the pin’s global EDB object ID, or the corresponding PadstackInstance object.
reference_pinsint, str, PadstackInstance, or list, optional: Reference pin specifier(s) or instance(s) for the port reference terminal. Allowed values are the same as for pins.
impedancestr or float, optional: Port impedance. The default is "50ohm".
port_namestr, optional: Port name. The default is None, in which case a name is automatically assigned.
pec_boundarybool, optional: Whether to define the PEC boundary. The default is False. If True, a perfect short is created between the pins and impedance is ignored. Only supported on a port created between two pins (no pin group).
pingroup_on_single_pinbool, optional: If True, force pin group definition on a single pin so the port is created at the pad center. If False, the port is created at the pad edge. The default is False.

Returns:

PadstackInstanceTerminal or bool: Created terminal object, or False if creation failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb(path_to_edb_file)
>>> pin = "AJ6"
>>> ref_pins = ["AM7", "AM4"]
>>> # Or take all reference pins on GND net
>>> ref_pins = [pin for pin in list(edb.components["U2A5"].pins.values()) if pin.net_name == "GND"]
>>> edb.components.create_port_on_pins(refdes="U2A5", pins=pin, reference_pins=ref_pins)
>>> edb.save()
>>> edb.close()

SourceExcitation.create_port_on_component(component: str | pyedb.grpc.database.components.Component, net_list: str | List[str], port_type: str = 'coax_port', do_pingroup: bool | None = True, reference_net: str | None = None, port_name: List[str] | None = None, solder_balls_height: float | str = None, solder_balls_size: float | str = None, solder_balls_mid_size: float | str = None, extend_reference_pins_outside_component: bool | None = False) → List[str]#

Create ports on a component.

Parameters:

componentstr or Component: EDB component or str component name.
net_liststr or list of string.: List of nets where ports must be created on the component. If the net is not part of the component, this parameter is skipped.
port_typestr, optional: Type of port to create. coax_port generates solder balls. circuit_port generates circuit ports on pins belonging to the net list.
do_pingroupbool: True activate pingroup during port creation (only used with combination of CircPort), False will take the closest reference pin and generate one port per signal pin.
reference_netstr or list of string.: list of the reference net.
port_namestr: Port name for overwriting the default port-naming convention, which is [component][net][pin]. The port name must be unique. If a port with the specified name already exists, the default naming convention is used so that port creation does not fail.
solder_balls_heightfloat, optional: Solder balls height used for the component. When provided default value is overwritten and must be provided in meter.
solder_balls_sizefloat, optional: Solder balls diameter. When provided auto evaluation based on padstack size will be disabled.
solder_balls_mid_sizefloat, optional: Solder balls mid-diameter. When provided if value is different than solder balls size, spheroid shape will be switched.
extend_reference_pins_outside_componentbool: When no reference pins are found on the component extend the pins search with taking the closest one. If do_pingroup is True will be set to False. Default value is False.

Returns:

double, bool: Salder ball height vale, False when failed.

Examples

>>> from pyedb import Edb
>>> edbapp = Edb("myaedbfolder")
>>> net_list = ["M_DQ<1>", "M_DQ<2>", "M_DQ<3>", "M_DQ<4>", "M_DQ<5>"]
>>> edbapp.excitations.create_port_on_component(cmp="U2A5", net_list=net_list,
>>> port_type=SourceType.CoaxPort, do_pingroup=False, refnet="GND")

SourceExcitation.add_port_on_rlc_component(component: str | pyedb.grpc.database.components.Component | None = None, circuit_ports: bool = True, pec_boundary: bool = False) → bool#

Deactivate RLC component and replace it with a circuit port. The circuit port supports only two-pin components.

Parameters:

componentstr: Reference designator of the RLC component.
circuit_portsbool: True will replace RLC component by circuit ports, False gap ports compatible with HFSS 3D modeler export.
pec_boundarybool, optional: Whether to define the PEC boundary, The default is False. If set to True, a perfect short is created between the pin and impedance is ignored. This parameter is only supported on a port created between two pins, such as when there is no pin group.

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.add_port_on_rlc_component("R1")

SourceExcitation.add_rlc_boundary(component: str | pyedb.grpc.database.components.Component | None = None, circuit_type: bool = True) → bool#

Add RLC gap boundary on component and replace it with a circuit port. The circuit port supports only 2-pin components.

Parameters:

componentstr: Reference designator of the RLC component.
circuit_typebool: When True circuit type are defined, if False gap type will be used instead (compatible with HFSS 3D modeler). Default value is True.

Returns:

bool: True when successful, False when failed.

SourceExcitation.create_coax_port(padstackinstance: pyedb.grpc.database.primitive.padstack_instance.PadstackInstance | int, use_dot_separator: bool = True, name: str | None = None, create_on_top: bool = True) → str | None#

Create HFSS 3Dlayout coaxial lumped port on a pastack Requires to have solder ball defined before calling this method.

Parameters:

padstackinstanceEdb.Cell.Primitive.PadstackInstance or int: Padstack instance object.
use_dot_separatorbool, optional: Whether to use . as the separator for the naming convention, which is [component][net][pin]. The default is True. If False, _ is used as the separator instead.
namestr: Port name for overwriting the default port-naming convention, which is [component][net][pin]. The port name must be unique. If a port with the specified name already exists, the default naming convention is used so that port creation does not fail.

Returns:

str: Terminal name.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin = edb.padstacks.instances[0]
>>> edb.excitation_manager.create_coax_port(pin, name="CoaxPort1")

SourceExcitation.create_circuit_port_on_pin(pos_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, neg_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, impedance: int | float = 50, port_name: str | None = None) → str | None#

Create a circuit port on a pin.

Parameters:

pos_pinObject: Edb Pin
neg_pinObject: Edb Pin
impedancefloat: Port Impedance
port_namestr, optional: Port Name

Returns:

str: Port Name.

Examples

>>> from pyedb import Edb
>>> edbapp = Edb("myaedbfolder", "project name", "release version")
>>> pins = edbapp.components.get_pin_from_component("U2A5")
>>> edbapp.excitation_manager.create_circuit_port_on_pin(pins[0], pins[1], 50, "port_name")

SourceExcitation.create_voltage_source_on_pin(pos_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, neg_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, voltage_value: int | float = 0, phase_value: int | float = 0, source_name: str | None = None) → str | None#

Create a voltage source.

Parameters:

pos_pinObject: Positive Pin.
neg_pinObject: Negative Pin.
voltage_valuefloat, optional: Value for the voltage. The default is 3.3.
phase_valueoptional: Value for the phase. The default is 0.
source_namestr, optional: Name of the source. The default is "".

Returns:

str: Source Name.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin1 = edb.components["U1"].pins["VCC"]
>>> pin2 = edb.components["U1"].pins["GND"]
>>> edb.excitation_manager.create_voltage_source_on_pin(pin1, pin2, 3.3, name="VSource1")

SourceExcitation.create_current_source_on_pin(pos_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, neg_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, current_value: int | float = 0, phase_value: int | float = 0, source_name: str | None = None) → str | None#

Create a voltage source.

Parameters:

pos_pinObject: Positive Pin.
neg_pinObject: Negative Pin.
voltage_valuefloat, optional: Value for the voltage. The default is 3.3.
phase_valueoptional: Value for the phase. The default is 0.
source_namestr, optional: Name of the source. The default is "".

Returns:

str: Source Name.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin1 = edb.components["U1"].pins["IN"]
>>> pin2 = edb.components["U1"].pins["GND"]
>>> edb.excitation_manager.create_current_source_on_pin(pin1, pin2, 0.1, name="ISource1")

SourceExcitation.create_resistor_on_pin(pos_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, neg_pin: str | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, rvalue: int | float = 1, resistor_name: str | None = '') → str | None#

Create a Resistor boundary between two given pins..

Parameters:

pos_pinObject: Positive Pin.
neg_pinObject: Negative Pin.
rvaluefloat, optional: Resistance value. The default is 1.
resistor_namestr, optional: Name of the resistor. The default is "".

Returns:

str: Name of the resistor.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin1 = edb.components["U1"].pins["R1_p"]
>>> pin2 = edb.components["U1"].pins["R1_n"]
>>> edb.excitation_manager.create_resistor_on_pin(pin1, pin2, 50, "R1")

SourceExcitation.create_circuit_port_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: str = None, negative_net_name: str | None = None, impedance_value: int | float = 50, port_name: str | None = None) → str | None#

Create a circuit port on a NET.

It groups all pins belonging to the specified net and then applies the port on PinGroups.

Parameters:

positive_component_namestr: Name of the positive component.
positive_net_namestr: Name of the positive net.
negative_component_namestr, optional: Name of the negative component. The default is None, in which case the name of the positive net is assigned.
negative_net_namestr, optional: Name of the negative net name. The default is None which will look for GND Nets.
impedance_valuefloat, optional: Port impedance value. The default is 50.
port_namestr, optional: Name of the port. The default is "".

Returns:

str: The name of the port.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_circuit_port_on_net("U1", "VCC", "U1", "GND", 50, "PowerPort")

SourceExcitation.create_voltage_source_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: str | None = None, negative_net_name: str | None = None, voltage_value: int | float = 0, phase_value: int | float = 0, source_name: str | None = None) → str | None#

Create a voltage source.

Parameters:

positive_component_namestr: Name of the positive component.
positive_net_namestr: Name of the positive net.
negative_component_namestr, optional: Name of the negative component. The default is None, in which case the name of the positive net is assigned.
negative_net_namestr, optional: Name of the negative net name. The default is None which will look for GND Nets.
voltage_valuefloat, optional: Value for the voltage. The default is 3.3.
phase_valueoptional: Value for the phase. The default is 0.
source_namestr, optional: Name of the source. The default is "".

Returns:

str: The name of the source.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_voltage_source_on_net("U1", "VCC", "U1", "GND", 3.3, name="VCC_Source")

SourceExcitation.create_current_source_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: str | None = None, negative_net_name: str | None = None, current_value: int | float = 0, phase_value: int | float = 0, source_name: str | None = None) → str | None#

Create a voltage source.

Parameters:

positive_component_namestr: Name of the positive component.
positive_net_namestr: Name of the positive net.
negative_component_namestr, optional: Name of the negative component. The default is None, in which case the name of the positive net is assigned.
negative_net_namestr, optional: Name of the negative net name. The default is None which will look for GND Nets.
voltage_valuefloat, optional: Value for the voltage. The default is 3.3.
phase_valueoptional: Value for the phase. The default is 0.
source_namestr, optional: Name of the source. The default is "".

Returns:

str: The name of the source.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_current_source_on_net("U1", "INPUT", "U1", "GND", 0.1, name="InputCurrent")
"InputCurrent"

SourceExcitation.create_coax_port_on_component(ref_des_list: str | List[str], net_list: str | List[str], delete_existing_terminal: bool = False) → List[str]#

Create a coaxial port on a component or component list on a net or net list.: The name of the new coaxial port is automatically assigned.

Parameters:

ref_des_listlist, str: List of one or more reference designators.
net_listlist, str: List of one or more nets.
delete_existing_terminalbool: Delete existing terminal with same name if exists. Port naming convention is ref_des`_`pin.net.name`_`pin.name

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_coax_port_on_component(["U1"], ["RF1", "RF2"])

SourceExcitation.check_before_terminal_assignement(connectable: Any, delete_existing_terminal: bool = False) → bool#

SourceExcitation.create_differential_wave_port(positive_primitive_id: int | pyedb.grpc.database.primitive.primitive.Primitive, positive_points_on_edge: List[float], negative_primitive_id: int | pyedb.grpc.database.primitive.primitive.Primitive, negative_points_on_edge: List[float], port_name: str | None = None, horizontal_extent_factor: int | float = 5, vertical_extent_factor: int | float = 3, pec_launch_width: str = '0.01mm') → pyedb.grpc.database.terminal.bundle_terminal.BundleTerminal#

Create a differential wave port.

Parameters:

positive_primitive_idint, EDBPrimitives: Primitive ID of the positive terminal.
positive_points_on_edgelist: Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge.
negative_primitive_idint, EDBPrimitives: Primitive ID of the negative terminal.
negative_points_on_edgelist: Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge.
port_namestr, optional: Name of the port. The default is None.
horizontal_extent_factorint, float, optional: Horizontal extent factor. The default value is 5.
vertical_extent_factorint, float, optional: Vertical extent factor. The default value is 3.
pec_launch_widthstr, optional: Launch Width of PEC. The default value is "0.01mm".

Returns:

tuple[str, object]: Tuple of (port_name, differential_port) where port_name is the name of the created port and differential_port is the port object.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> port_name, port = edb.excitation_manager.create_differential_wave_port(0, [0, 0], 1, [0, 0.2])

SourceExcitation.create_horizontal_wave_port(void: int | pyedb.grpc.database.primitive.primitive.Primitive, padstack_instances: list[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance] = None, pec_launch_width: str = '0.04mm', layer_alignment: str = 'Lower') → bool | pyedb.grpc.database.terminal.bundle_terminal.BundleTerminal#

Create a horizontal wave port around one or more vias inside a void.

A horizontal wave port is a higher-fidelity alternative to coaxial lumped ports for vertical interconnect excitation. Unlike a gap or lumped port, which assumes a uniform current distribution, a wave port solves the field distribution at the launch and therefore captures a more realistic characteristic impedance. This usually improves the evaluation of fringing fields and can noticeably affect results for differential pairs and other high-speed channel structures.

Parameters:

voidint | Primitive: Void primitive, or void primitive ID, used to define the horizontal wave-port reference contour.
padstack_instanceslist[PadstackInstance], optional: Padstack instances to connect to the horizontal wave port. When not provided, padstack instances are automatically detected from the vias intersecting the void polygon.
pec_launch_widthstr, optional: PEC launch width assigned to the HFSS solver option. The default is "0.04mm".
layer_alignmentstr, optional: HFSS layer alignment for the wave port. Typical values are "Lower" and "Upper". The default is "Lower".

Returns:

bool | BundleTerminal: Bundle terminal representing the created horizontal wave port. If no padstack instance is found inside the target void, False is returned.

Notes

Horizontal wave ports can be used in place of coaxial lumped ports when a more physical launch model is required. Because the wave port computes the electromagnetic field distribution, it produces a more realistic impedance than gap-port formulations that assume uniform current. This also improves fringing-field estimation and can have a significant impact on extracted results for differential links and other high-speed interconnect channels.

SourceExcitation.create_wave_port(prim_id: int | pyedb.grpc.database.primitive.primitive.Primitive, point_on_edge: List[float], port_name: str | None = None, impedance: int | float = 50, horizontal_extent_factor: int | float = 5, vertical_extent_factor: int | float = 3, pec_launch_width: str = '0.01mm') → Tuple[str, pyedb.grpc.database.ports.ports.WavePort]#

Create a wave port.

Parameters:

prim_idint, Primitive: Primitive ID.
point_on_edgelist: Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge.
port_namestr, optional: Name of the port. The default is None.
impedanceint, float, optional: Impedance of the port. The default value is 50.
horizontal_extent_factorint, float, optional: Horizontal extent factor. The default value is 5.
vertical_extent_factorint, float, optional: Vertical extent factor. The default value is 3.
pec_launch_widthstr, optional: Launch Width of PEC. The default value is "0.01mm".

Returns:

tuple[str, object]: Tuple of (port_name, port) where port_name is the name of the created wave port and port is the port object.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> port_name, port = edb.excitation_manager.create_wave_port(0, [0, 0])

SourceExcitation.create_edge_port_vertical(prim_id: int, point_on_edge: List[float], port_name: str | None = None, impedance: int | float = 50, reference_layer: str | None = None, hfss_type: str = 'Gap', horizontal_extent_factor: int | float = 5, vertical_extent_factor: int | float = 3, pec_launch_width: str = '0.01mm') → str | None#

Create a vertical edge port.

Parameters:

prim_idint: Primitive ID.
point_on_edgelist: Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge.
port_namestr, optional: Name of the port. The default is None.
impedanceint, float, optional: Impedance of the port. The default value is 50.
reference_layerstr, optional: Reference layer of the port. The default is None.
hfss_typestr, optional: Type of the port. The default value is "Gap". Options are "Gap", "Wave".
horizontal_extent_factorint, float, optional: Horizontal extent factor. The default value is 5.
vertical_extent_factorint, float, optional: Vertical extent factor. The default value is 3.
radial_extent_factorint, float, optional: Radial extent factor. The default value is 0.
pec_launch_widthstr, optional: Launch Width of PEC. The default value is "0.01mm".

Returns:

str: Port name.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> term = edb.excitation_manager.create_edge_port_vertical(0, [0, 0], reference_layer="TopLayer")

SourceExcitation.create_edge_port_horizontal(prim_id: int | pyedb.grpc.database.primitive.primitive.Primitive, point_on_edge: List[float], ref_prim_id: int | pyedb.grpc.database.primitive.primitive.Primitive | None = None, point_on_ref_edge: List[float] | None = None, port_name: str | None = None, impedance: int | float = 50, layer_alignment: str = 'Upper') → pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal | None#

Create a horizontal edge port.

Parameters:

prim_idint: Primitive ID.
point_on_edgelist: Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge.
ref_prim_idint, optional: Reference primitive ID. The default is None.
point_on_ref_edgelist, optional: Coordinate of the point to define the reference edge terminal. The point must be on the target edge but not on the two ends of the edge. The default is None.
port_namestr, optional: Name of the port. The default is None.
impedanceint, float, optional: Impedance of the port. The default value is 50.
layer_alignmentstr, optional: Layer alignment. The default value is Upper. Options are "Upper", "Lower".

Returns:

str: Name of the port.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_edge_port_horizontal(0, [0, 0], 1, [0, 0.1], "EdgePort")

SourceExcitation.create_lumped_port_on_net(nets: str | List[str] | None = None, reference_layer: str | pyedb.grpc.database.layers.stackup_layer.StackupLayer | None = None, return_points_only: bool = False, digit_resolution: int = 6, at_bounding_box: bool = True) → bool#

Create an edge port on nets. This command looks for traces and polygons on the nets and tries to assign vertical lumped port.

Parameters:

netslist, optional

List of nets, str or Edb net.

reference_layerstr, Edb layer.

Name or Edb layer object.

return_points_onlybool, optional

Use this boolean when you want to return only the points from the edges and not creating ports. Default value is False.

digit_resolutionint, optional

The number of digits carried for the edge location accuracy. The default value is 6.

at_bounding_boxbool

When True will keep the edges from traces at the layout bounding box location. This is recommended when: a cutout has been performed before and lumped ports have to be created on ending traces. Default value is True.

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> points = edb.excitation_manager.create_lumped_port_on_net(["Net1"], return_points_only=True)

Create an edge port on clipped signal traces.

Parameters:

netslist, optional: String of one net or EDB net or a list of multiple nets or EDB nets.
reference_netstr, Edb net.: Name or EDB reference net.
user_defined_extent[x, y], EDB PolygonData: Use this point list or PolygonData object to check if ports are at this polygon border.

Returns:

list[list[str]]: Nested list where each entry is [net_name, x, y, terminal_name] for each port placed at the polygon border.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> terminals = edb.excitation_manager.create_vertical_circuit_port_on_clipped_traces(["Net1"], "GND")

SourceExcitation.create_bundle_wave_port(primitives_id: List[int | pyedb.grpc.database.primitive.primitive.Primitive], points_on_edge: List[List[float]], port_name: str | None = None, horizontal_extent_factor: int | float = 5, vertical_extent_factor: int | float = 3, pec_launch_width: str = '0.01mm') → pyedb.grpc.database.ports.ports.BundleWavePort#

Create a bundle wave port.

Parameters:

primitives_idlist: Primitive ID of the positive terminal.
points_on_edgelist: Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge.
port_namestr, optional: Name of the port. The default is None.
horizontal_extent_factorint, float, optional: Horizontal extent factor. The default value is 5.
vertical_extent_factorint, float, optional: Vertical extent factor. The default value is 3.
pec_launch_widthstr, optional: Launch Width of PEC. The default value is "0.01mm".

Returns:

tuple[str, object]: Tuple of (port_name, bundle_port) where port_name is the name of the created bundle wave port and bundle_port is the port object.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> port_name, port = edb.excitation_manager.create_bundle_wave_port([0, 1], [[0, 0], [0, 0.2]])

SourceExcitation.create_hfss_ports_on_padstack(pinpos: pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, portname: str | None = None) → bool#

Create an HFSS port on a padstack.

Parameters:

pinpos: Position of the pin.
portnamestr, optional: Name of the port. The default is None.

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin = edb.padstacks.instances[0]
>>> edb.excitation_manager.create_hfss_ports_on_padstack(pin, "Port1")

SourceExcitation.get_ports_number() → int#

Return the total number of excitation ports in a layout.

Parameters:

None

Returns:

int: Number of ports.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> num_ports = edb.excitation_manager.get_ports_number()

SourceExcitation.get_point_terminal(name: str, net_name: str, location: List[float], layer: str) → pyedb.grpc.database.terminal.point_terminal.PointTerminal#

Place terminal between two points.

Parameters:

namestr,: Name of the terminal.
net_namestr: Name of the net.
locationlist: Location of the terminal.
layerstr,: Layer of the terminal.

Returns:

PointTerminal

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> term = edb.excitation_manager.get_point_terminal("Term1", "Net1", [0, 0], "TopLayer")

SourceExcitation.create_rlc_boundary_on_pins(positive_pin: pyedb.grpc.database.primitive.padstack_instance.PadstackInstance | None = None, negative_pin: pyedb.grpc.database.primitive.padstack_instance.PadstackInstance | None = None, rvalue: float = 0.0, lvalue: float = 0.0, cvalue: float = 0.0) → pyedb.grpc.database.terminal.terminal.Terminal | bool#

Create hfss rlc boundary on pins.

Parameters:

positive_pinPositive pin.: Edb.Cell.Primitive.PadstackInstance
negative_pinNegative pin.: Edb.Cell.Primitive.PadstackInstance
rvalueResistance value
lvalueInductance value
cvalue . Capacitance value.

Returns:

bool: True when successful, False when failed.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> pin1 = edb.components["U1"].pins["Pin1"]
>>> pin2 = edb.components["U1"].pins["Pin2"]
>>> term = edb.excitation_manager.create_rlc_boundary_on_pins(pin1, pin2, rvalue=50)

SourceExcitation.get_edge_from_port(port)#

SourceExcitation.create_edge_port(location, primitive_name, name, impedance=50, is_wave_port=True, horizontal_extent_factor=1, vertical_extent_factor=1, pec_launch_width=0.0001)#

SourceExcitation.create_edge_port_on_polygon(polygon: pyedb.grpc.database.primitive.primitive.Primitive | None = None, reference_polygon: pyedb.grpc.database.primitive.primitive.Primitive | None = None, terminal_point: List[float] | None = None, reference_point: List[float] | None = None, reference_layer: str | pyedb.grpc.database.layers.stackup_layer.StackupLayer | None = None, port_name: str | None = None, port_impedance: int | float = 50.0, force_circuit_port: bool = False) → str | None#

Create lumped port between two edges from two different polygons. Can also create a vertical port when the reference layer name is only provided. When a port is created between two edge from two polygons which don’t belong to the same layer, a circuit port will be automatically created instead of lumped. To enforce the circuit port instead of lumped,use the boolean force_circuit_port.

Parameters:

polygonPolygon: EDB polygon object used to assign the port.
reference_polygonPolygon: EDB polygon object used to define the port reference.
terminal_pointlist[float]: Coordinate [x, y] in meters of the point on the polygon edge where the port is placed. Taking the midpoint of an edge is recommended.
reference_pointlist[float], optional: Same as terminal_point but for defining the reference location on the reference polygon edge. Values in meters.
reference_layerstr, optional: Layer name used to define the port reference for vertical ports.
port_namestr, optional: Name of the port.
port_impedancefloat, optional: Port impedance in ohms. The default is 50.
force_circuit_portbool, optional: When True, force circuit port creation instead of lumped. Applies to both vertical and coplanar ports.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> poly = edb.modeler.primitives[0]
>>> ref_poly = edb.modeler.primitives[1]
>>> edb.excitation_manager.create_edge_port_on_polygon(poly, ref_poly, [0, 0], [0.1, 0])

Create circuit port between pin and a reference layer.

Parameters:

component_namestr: Component name. The default is None.
pins_namestr: Pin name or list of pin names. The default is None.
layer_namestr: Layer name. The default is None.
reference_netstr: Reference net name. The default is None.
impedancefloat, optional: Port impedance. The default is 50.0 in ohms.

Returns:

PadstackInstanceTerminal: Created terminal.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> terms = edb.excitation_manager.create_port_between_pin_and_layer("U1", "Pin1", "GND", "GND")

SourceExcitation.create_current_source(terminal: pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal | pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal, ref_terminal: pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal | pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal, magnitude: int | float = 1, phase: int | float = 0) → pyedb.grpc.database.terminal.terminal.Terminal | bool#

Create a current source.

Parameters:

terminalEdgeTerminalor: PadstackInstanceTerminal or PointTerminal or PinGroupTerminal.

Positive terminal of the source.
ref_terminalEdgeTerminal or: pyedb.grpc.database.terminals.PadstackInstanceTerminal or PadstackInstanceTerminal or PinGroupTerminal.

Negative terminal of the source.
magnitudeint, float, optional: Magnitude of the source.
phaseint, float, optional: Phase of the source

Returns:

ExcitationSources

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_current_source_on_pin_group("PG1", "PG2", 0.1, name="ISource1")

SourceExcitation.create_current_source_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, magnitude: int | float = 1, phase: int | float = 0, name: str | None = None) → bool#

Create current source between two pin groups.

Parameters:

pos_pin_group_namestr: Name of the positive pin group.
neg_pin_group_namestr: Name of the negative pin group.
magnitudeint, float, optional: Magnitude of the source.
phaseint, float, optional: Phase of the source

Returns:

bool

SourceExcitation.create_voltage_source(terminal: pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal | pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, ref_terminal: pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal | pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal | pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, magnitude: int | float = 1, phase: int | float = 0) → pyedb.grpc.database.terminal.terminal.Terminal | bool#

Create a voltage source.

Parameters:

namestr, optional: Voltage source name
terminalEdgeTerminal,: PadstackInstanceTerminal, PointTerminal, PinGroupTerminal, PadstackInstance, Positive terminal of the source.
ref_terminalEdgeTerminal,: pyedb.grpc.database.terminals.PadstackInstanceTerminal, PadstackInstanceTerminal, PinGroupTerminal, PadstackInstance, Negative terminal of the source.
magnitudeint, float, optional: Magnitude of the source.
phaseint, float, optional: Phase of the source

Returns:

class:ExcitationSources

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_voltage_source("pin1", "pin2", 3.3, name="VSource1")

SourceExcitation.create_voltage_source_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, magnitude: int | float = 1, phase: int | float = 0, name: str | None = None, impedance: int | float = 0.001) → bool#

Create voltage source between two pin groups.

Parameters:

pos_pin_group_namestr: Name of the positive pin group.
neg_pin_group_namestr: Name of the negative pin group.
magnitudeint, float, optional: Magnitude of the source.
phaseint, float, optional: Phase of the source

Returns:

bool

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_voltage_probe_on_pin_group("Probe1", "PG1", "PG2")

SourceExcitation.create_voltage_probe(terminal: pyedb.grpc.database.terminal.terminal.Terminal, ref_terminal: pyedb.grpc.database.terminal.terminal.Terminal) → pyedb.grpc.database.terminal.terminal.Terminal | bool#

Create a voltage probe.

Parameters:

terminalEdgeTerminal,: PadstackInstanceTerminal, PointTerminal, PinGroupTerminal, PadstackInstance, Positive terminal of the port.
ref_terminalEdgeTerminal,: pyedb.grpc.database.terminals.PadstackInstanceTerminal, PadstackInstanceTerminal, PinGroupTerminal, PadstackInstance, Negative terminal of the probe.

Returns:

Terminal

SourceExcitation.create_voltage_probe_on_pin_group(probe_name: str, pos_pin_group_name: str, neg_pin_group_name: str, impedance: int | float = 1000000) → bool#

Create voltage probe between two pin groups.

Parameters:

probe_namestr: Name of the probe.
pos_pin_group_namestr: Name of the positive pin group.
neg_pin_group_namestr: Name of the negative pin group.
impedanceint, float, optional: Phase of the source.

Returns:

bool

SourceExcitation.create_dc_terminal(component_name: str, net_name: str, source_name: str | None = None) → str | None#

Create a dc terminal.

Parameters:

component_namestr: Name of the positive component.
net_namestr: Name of the positive net.
source_namestr, optional: Name of the source. The default is "".

Returns:

str: The name of the source.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_dc_terminal("U1", "VCC", "DC_VCC")

SourceExcitation.create_circuit_port_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, impedance: int | float = 50, name: str | None = None) → bool#

Create a port between two pin groups.

Parameters:

pos_pin_group_namestr: Name of the positive pin group.
neg_pin_group_namestr: Name of the negative pin group.
impedanceint, float, optional: Impedance of the port. Default is 50.
namestr, optional: Port name.

Returns:

bool

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> edb.excitation_manager.create_circuit_port_on_pin_group("PG1", "PG2", 50, "Port1")

SourceExcitation.place_voltage_probe(name: str, positive_net_name: str, positive_location: List[float], positive_layer: str, negative_net_name: str, negative_location: List[float], negative_layer: str) → pyedb.grpc.database.terminal.terminal.Terminal#

Place a voltage probe between two points.

Parameters:

namestr: Name of the probe.
positive_net_namestr: Name of the positive net.
positive_locationlist[float]: Location [x, y] of the positive terminal.
positive_layerstr: Layer of the positive terminal.
negative_net_namestr: Name of the negative net.
negative_locationlist[float]: Location [x, y] of the negative terminal.
negative_layerstr: Layer of the negative terminal.

Returns:

Terminal: Created voltage probe terminal object.

Examples

>>> from pyedb import Edb
>>> edb = Edb()
>>> probe = edb.excitation_manager.place_voltage_probe(
...     "Probe1", "Net1", [0, 0], "TopLayer", "GND", [0.1, 0], "TopLayer"
... )

SourceExcitation.create_padstack_instance_terminal(name='', padstack_instance_id=None, padstack_instance_name=None)#

SourceExcitation.create_point_terminal(x, y, layer, net, name='')#

SourceExcitation.create_edge_terminal(primitive_name, x, y, name='')#

SourceExcitation.create_bundle_terminal(terminals, name='')#

SourceExcitation.create_pin_group_terminal(pin_group)#

SourceExcitation.create_terminal_from_pin_group(pin_group, name='')#

SourceExcitation#

Overview#

Import detail#

Property detail#

Method detail#

`SourceExcitation`#