:class:`SourceExcitation` ========================= .. py:class:: pyedb.grpc.database.source_excitations.SourceExcitation(pedb) Manage sources and excitations. .. rubric:: Examples >>> # Initialize EDB session >>> from pyedb import Edb >>> edb = Edb(edbpath="path/to/your/edb") >>> # Access SourceExcitation class >>> source_excitations = edb.source_excitation >>> # 1. create_source_on_component >>> # Create voltage source on component pins >>> from pyedb.grpc.database.utility.sources import Source, SourceType >>> source = Source( ... source_type=SourceType.Vsource, ... name="V1", ... positive_node=("U1", "VCC"), ... negative_node=("U1", "GND"), ... amplitude="1V", ... phase="0deg", ... impedance="50ohm", ... ) >>> source_excitations.create_source_on_component([source]) >>> # 2. create_port >>> # Create port between two terminals >>> pos_terminal = edb.terminals["MyTerminal"] >>> ref_terminal = edb.terminals["MyRefTerminal"] >>> port = source_excitations.create_port(pos_terminal, ref_terminal) >>> # 3. create_port_on_pins >>> # Create circuit port between component pins >>> port_term = source_excitations.create_port_on_pins( ... refdes="U1", pins="Pin1", reference_pins=["GND_Pin1", "GND_Pin2"], impedance=50, port_name="Port1" ... ) >>> # 4. create_port_on_component >>> # Create coaxial ports on component nets >>> source_excitations.create_port_on_component( ... component="U1", net_list=["PCIe_RX0", "PCIe_RX1"], port_type=SourceType.CoaxPort, reference_net="GND" ... ) >>> # 5. add_port_on_rlc_component >>> # Replace RLC component with circuit port >>> source_excitations.add_port_on_rlc_component("R1") >>> # 6. _create_terminal (Internal method - typically not called directly) >>> # 7. _create_pin_group_terminal (Internal method) >>> # 8. create_coax_port >>> # Create coaxial port on padstack >>> pin = edb.components["U1"].pins["Pin1"] >>> port_name = source_excitations.create_coax_port(pin) >>> # 9. create_circuit_port_on_pin >>> # Create circuit port between two pins >>> pin1 = edb.components["U1"].pins["Pin1"] >>> pin2 = edb.components["U1"].pins["Pin2"] >>> port_name = source_excitations.create_circuit_port_on_pin(pin1, pin2, 50, "Port1") >>> # 10. create_voltage_source_on_pin >>> # Create voltage source between pins >>> source_name = source_excitations.create_voltage_source_on_pin(pin1, pin2, 3.3, 0, "V1") >>> # 11. create_current_source_on_pin >>> # Create current source between pins >>> source_name = source_excitations.create_current_source_on_pin(pin1, pin2, 0.1, 0, "I1") >>> # 12. create_resistor_on_pin >>> # Create resistor between pins >>> res_name = source_excitations.create_resistor_on_pin(pin1, pin2, 100, "R1") >>> # 13. create_circuit_port_on_net >>> # Create port between component nets >>> port_name = source_excitations.create_circuit_port_on_net( >>> "U1", "SignalNet", "U1", "GND", 50, "Port1" >>> ) >>> # 14. create_voltage_source_on_net >>> # Create voltage source between nets >>> source_name = source_excitations.create_voltage_source_on_net( >>> "U1", "VCC", "U1", "GND", 5.0, 0, "VCC_Source" >>> ) >>> # 15. create_current_source_on_net >>> # Create current source between nets >>> source_name = source_excitations.create_current_source_on_net( >>> "U1", "InputNet", "U1", "GND", 0.02, 0, "InputCurrent" >>> ) >>> # 16. create_coax_port_on_component >>> # Create coaxial ports on component >>> ports = source_excitations.create_coax_port_on_component( ... ["U1", "U2"], ["PCIe_RX0", "PCIe_TX0"], delete_existing_terminal=True ... ) >>> # 17. create_differential_wave_port >>> # Create differential wave port >>> pos_prim = edb.modeler.primitives[0] >>> neg_prim = edb.modeler.primitives[1] >>> port_name, diff_port = source_excitations.create_differential_wave_port( ... pos_prim.id, [0, 0], neg_prim.id, [0, 0.2], "DiffPort" ... ) >>> # 18. create_wave_port >>> # Create wave port >>> port_name, wave_port = source_excitations.create_wave_port(pos_prim.id, [0, 0], "WavePort") >>> # 19. create_bundle_wave_port >>> # Create bundle wave port >>> port_name, bundle_port = source_excitations.create_bundle_wave_port( ... [pos_prim.id, neg_prim.id], [[0, 0], [0, 0.2]], "BundlePort" ... ) >>> # 20. create_dc_terminal >>> # Create DC terminal >>> source_excitations.create_dc_terminal("U1", "VCC", "VCC_Terminal") >>> # 21. create_voltage_probe >>> # Create voltage probe >>> probe = source_excitations.create_voltage_probe(term1, term2) >>> # 22. place_voltage_probe >>> # Place voltage probe between points >>> source_excitations.place_voltage_probe( ... "Probe1", "SignalNet", [0, 0], "TopLayer", "GND", [0.1, 0.1], "BottomLayer" ... ) >>> # Save and close EDB >>> edb.save() >>> edb.close() .. !! processed by numpydoc !! .. py:currentmodule:: SourceExcitation Overview -------- .. tab-set:: .. tab-item:: Methods .. list-table:: :header-rows: 0 :widths: auto * - :py:attr:`~create_source_on_component` - Create voltage, current source, or resistor on component. * - :py:attr:`~create_port` - Create a port. * - :py:attr:`~create_port_on_pins` - Create circuit port between pins and reference ones. * - :py:attr:`~create_port_on_component` - Create ports on a component. * - :py:attr:`~add_port_on_rlc_component` - Deactivate RLC component and replace it with a circuit port. * - :py:attr:`~add_rlc_boundary` - Add RLC gap boundary on component and replace it with a circuit port. * - :py:attr:`~create_coax_port` - Create HFSS 3Dlayout coaxial lumped port on a pastack * - :py:attr:`~create_circuit_port_on_pin` - Create a circuit port on a pin. * - :py:attr:`~create_voltage_source_on_pin` - Create a voltage source. * - :py:attr:`~create_current_source_on_pin` - Create a voltage source. * - :py:attr:`~create_resistor_on_pin` - Create a Resistor boundary between two given pins.. * - :py:attr:`~create_circuit_port_on_net` - Create a circuit port on a NET. * - :py:attr:`~create_pin_group_terminal` - Create a pin group terminal. * - :py:attr:`~create_voltage_source_on_net` - Create a voltage source. * - :py:attr:`~create_current_source_on_net` - Create a voltage source. * - :py:attr:`~create_coax_port_on_component` - Create a coaxial port on a component or component list on a net or net list. * - :py:attr:`~check_before_terminal_assignement` - * - :py:attr:`~create_differential_wave_port` - Create a differential wave port. * - :py:attr:`~create_wave_port` - Create a wave port. * - :py:attr:`~create_edge_port_vertical` - Create a vertical edge port. * - :py:attr:`~create_edge_port_horizontal` - Create a horizontal edge port. * - :py:attr:`~create_lumped_port_on_net` - Create an edge port on nets. This command looks for traces and polygons on the * - :py:attr:`~create_vertical_circuit_port_on_clipped_traces` - Create an edge port on clipped signal traces. * - :py:attr:`~create_bundle_wave_port` - Create a bundle wave port. * - :py:attr:`~create_hfss_ports_on_padstack` - Create an HFSS port on a padstack. * - :py:attr:`~get_ports_number` - Return the total number of excitation ports in a layout. * - :py:attr:`~get_point_terminal` - Place terminal between two points. * - :py:attr:`~create_rlc_boundary_on_pins` - Create hfss rlc boundary on pins. * - :py:attr:`~create_edge_port_on_polygon` - Create lumped port between two edges from two different polygons. Can also create a vertical port when * - :py:attr:`~create_port_between_pin_and_layer` - Create circuit port between pin and a reference layer. * - :py:attr:`~create_current_source` - Create a current source. * - :py:attr:`~create_current_source_on_pin_group` - Create current source between two pin groups. * - :py:attr:`~create_voltage_source` - Create a voltage source. * - :py:attr:`~create_voltage_source_on_pin_group` - Create voltage source between two pin groups. * - :py:attr:`~create_voltage_probe` - Create a voltage probe. * - :py:attr:`~create_voltage_probe_on_pin_group` - Create voltage probe between two pin groups. * - :py:attr:`~create_dc_terminal` - Create a dc terminal. * - :py:attr:`~create_circuit_port_on_pin_group` - Create a port between two pin groups. * - :py:attr:`~place_voltage_probe` - Place a voltage probe between two points. .. tab-item:: Properties .. list-table:: :header-rows: 0 :widths: auto * - :py:attr:`~excitations` - Get all excitations. * - :py:attr:`~sources` - Get all sources. * - :py:attr:`~probes` - Get all probes. Import detail ------------- .. code-block:: python from pyedb.grpc.database.source_excitations import SourceExcitation Property detail --------------- .. py:property:: excitations :type: Dict[str, Any] Get all excitations. .. !! processed by numpydoc !! .. py:property:: sources :type: Dict[str, Any] Get all sources. .. !! processed by numpydoc !! .. py:property:: probes :type: Dict[str, Any] Get all probes. .. !! processed by numpydoc !! Method detail ------------- .. py:method:: create_source_on_component(sources: Optional[Union[pyedb.grpc.database.utility.sources.Source, List[pyedb.grpc.database.utility.sources.Source]]] = None) -> bool Create voltage, current source, or resistor on component. :Parameters: **sources** : :class:`python:list`\[:obj:`Source`] List of ``pyedb.grpc.utility.sources.Source`` objects. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> from pyedb.grpc.utility.sources import Source, SourceType >>> edb = Edb() >>> source = Source(source_type=SourceType.Vsource, amplitude="1V", ...) >>> edb.source_excitation.create_source_on_component([source]) .. !! processed by numpydoc !! .. py:method:: create_port(terminal: pyedb.grpc.database.terminal.terminal.Terminal, ref_terminal: Optional[pyedb.grpc.database.terminal.terminal.Terminal] = None, is_circuit_port: bool = False, name: Optional[str] = None) -> Any Create a port. :Parameters: **terminal** : class:`pyedb.dotnet.database.edb_data.terminals.EdgeTerminal`, class:`pyedb.grpc.database.terminals.PadstackInstanceTerminal`, class:`pyedb.grpc.database.terminals.PointTerminal`, class:`pyedb.grpc.database.terminals.PinGroupTerminal`, Positive terminal of the port. **ref_terminal** : class:`pyedb.grpc.database.terminals.EdgeTerminal`, class:`pyedb.grpc.database.terminals.PadstackInstanceTerminal`, class:`pyedb.grpc.database.terminals.PointTerminal`, class:`pyedb.grpc.database.terminals.PinGroupTerminal`, optional Negative terminal of the port. **is_circuit_port** : :ref:`bool `, :obj:`optional` Whether it is a circuit port. The default is ``False``. **name: str, optional** Name of the created port. The default is None, a random name is generated. **Returns** .. **-------** .. **list: [:class:`GapPort ,** :class:`WavePort `]. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> term = edb.terminals["MyTerminal"] >>> ref_term = edb.terminals["RefTerminal"] >>> port = edb.source_excitation.create_port(term, ref_term, name="Port1") .. !! processed by numpydoc !! .. py:method:: create_port_on_pins(refdes: Union[str, pyedb.grpc.database.components.Component], pins: Union[int, str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, List[Union[int, str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance]]], reference_pins: Union[int, str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, List[Union[int, str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance]]] = None, impedance: Union[str, float] = '50ohm', port_name: Optional[str] = None, pec_boundary: bool = False, pingroup_on_single_pin: bool = False) -> pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal Create circuit port between pins and reference ones. :Parameters: **refdes** : :obj:`Component` :obj:`reference` :obj:`designator` str or Component object. **pins** : :obj:`pin` :obj:`specifier`\(:obj:`s`) :obj:`or` :obj:`instance`\(:obj:`s`) :obj:`where` :obj:`the` :obj:`port` :obj:`terminal` :obj:`is` :obj:`to` :obj:`be` created. :obj:`Single` :obj:`pin` :obj:`name` or :obj:`a` :class:`python:list` :obj:`of` .. **several can be provided. If several pins are provided a pin group will be created. Pin specifiers can be the** .. **global EDB object ID or padstack instance name or pin name on component with refdes ``refdes``. Pin instances** .. **can be provided as ``EDBPadstackInstance`` objects.** .. **For instance for the pin called ``Pin1`` located on component with refdes ``U1``: ``U1-Pin1``, ``Pin1`` with** .. **``refdes=U1``, the pin's global EDB object ID, or the ``EDBPadstackInstance`` corresponding to the pin can be** .. **provided.** Union[int, str, PadstackInstance], List[Union[int, str, PadstackInstance]] **reference_pins** : :obj:`reference` :obj:`pin` :obj:`specifier`\(:obj:`s`) :obj:`or` :obj:`instance`\(:obj:`s`) :obj:`for` :obj:`the` :obj:`port` :obj:`reference` terminal. :obj:`Allowed` :obj:`values` :obj:`are` .. **the same as for the ``pins`` parameter.** Union[int, str, PadstackInstance], List[Union[int, str, PadstackInstance]] **impedance** : :obj:`Port` :obj:`impedance` str, float **port_name** : :class:`python:str`, :obj:`optional` Port name. The default is ``None``, in which case a name is automatically assigned. **pec_boundary** : :ref:`bool `, :obj:`optional` .. **Whether to define the PEC boundary, The default is ``False``. If set to ``True``,** .. **a perfect short is created between the pin and impedance is ignored. This** .. **parameter is only supported on a port created between two pins, such as** .. **when there is no pin group.** .. **pingroup_on_single_pin** : :ref:`bool ` If ``True`` force using pingroup definition on single pin to have the port created at the pad center. If ``False`` the port is created at the pad edge. Default value is ``False``. :Returns: :obj:`EDB` :obj:`terminal` :obj:`created`, :obj:`or` :data:`python:False` :obj:`if` :obj:`failed` :obj:`to` create. .. Example: .. >>> :obj:`from` :obj:`pyedb` :obj:`import` :obj:`Edb` .. >>> :obj:`edb` = :obj:`Edb`\(:obj:`path_to_edb_file`) .. >>> :obj:`pin` = "AJ6" .. >>> :obj:`ref_pins` = ["AM7", "AM4"] .. :obj:`Or` :obj:`to` :obj:`take` :obj:`all` :obj:`reference` :obj:`pins` .. >>> :obj:`ref_pins` = [:obj:`pin` :obj:`for` :obj:`pin` :obj:`in` :class:`python:list`\(:obj:`edb.components`\["U2A5"]:obj:`.pins.values`\()) :obj:`if` :obj:`pin.net_name` == "GND"] .. >>> :obj:`edb.components.create_port_on_pins`\(refdes="U2A5", pins=pin, reference_pins=ref_pins) .. >>> :obj:`edb.save_edb`\() .. >>> :obj:`edb.close_edb`\() .. .. !! processed by numpydoc !! .. py:method:: create_port_on_component(component: Union[str, pyedb.grpc.database.components.Component], net_list: Union[str, List[str]], port_type: str = 'coax_port', do_pingroup: Optional[bool] = True, reference_net: Optional[str] = None, port_name: Optional[List[str]] = None, solder_balls_height: Union[float, str] = None, solder_balls_size: Union[float, str] = None, solder_balls_mid_size: Union[float, str] = None, extend_reference_pins_outside_component: Optional[bool] = False) -> List[str] Create ports on a component. :Parameters: **component** : :class:`python:str` or :obj:`Component` EDB component or str component name. **net_list** : :class:`python:str` or :class:`python:list` :obj:`of` string. List of nets where ports must be created on the component. If the net is not part of the component, this parameter is skipped. **port_type** : :class:`python:str`, :obj:`optional` Type of port to create. ``coax_port`` generates solder balls. ``circuit_port`` generates circuit ports on pins belonging to the net list. **do_pingroup** : :ref:`bool ` True activate pingroup during port creation (only used with combination of CircPort), False will take the closest reference pin and generate one port per signal pin. **reference_net** : :class:`python:str` or :class:`python:list` :obj:`of` string. list of the reference net. **port_name** : :class:`python:str` Port name for overwriting the default port-naming convention, which is ``[component][net][pin]``. The port name must be unique. If a port with the specified name already exists, the default naming convention is used so that port creation does not fail. **solder_balls_height** : :class:`python:float`, :obj:`optional` Solder balls height used for the component. When provided default value is overwritten and must be provided in meter. **solder_balls_size** : :class:`python:float`, :obj:`optional` Solder balls diameter. When provided auto evaluation based on padstack size will be disabled. **solder_balls_mid_size** : :class:`python:float`, :obj:`optional` Solder balls mid-diameter. When provided if value is different than solder balls size, spheroid shape will be switched. **extend_reference_pins_outside_component** : :ref:`bool ` When no reference pins are found on the component extend the pins search with taking the closest one. If `do_pingroup` is `True` will be set to `False`. Default value is `False`. :Returns: :obj:`double`, :ref:`bool ` Salder ball height vale, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edbapp = Edb("myaedbfolder") >>> net_list = ["M_DQ<1>", "M_DQ<2>", "M_DQ<3>", "M_DQ<4>", "M_DQ<5>"] >>> edbapp.excitations.create_port_on_component(cmp="U2A5", net_list=net_list, >>> port_type=SourceType.CoaxPort, do_pingroup=False, refnet="GND") .. !! processed by numpydoc !! .. py:method:: add_port_on_rlc_component(component: Optional[Union[str, pyedb.grpc.database.components.Component]] = None, circuit_ports: bool = True, pec_boundary: bool = False) -> bool Deactivate RLC component and replace it with a circuit port. The circuit port supports only two-pin components. :Parameters: **component** : :class:`python:str` Reference designator of the RLC component. **circuit_ports** : :ref:`bool ` ``True`` will replace RLC component by circuit ports, ``False`` gap ports compatible with HFSS 3D modeler export. **pec_boundary** : :ref:`bool `, :obj:`optional` Whether to define the PEC boundary, The default is ``False``. If set to ``True``, a perfect short is created between the pin and impedance is ignored. This parameter is only supported on a port created between two pins, such as when there is no pin group. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.add_port_on_rlc_component("R1") .. !! processed by numpydoc !! .. py:method:: add_rlc_boundary(component: Optional[Union[str, pyedb.grpc.database.components.Component]] = None, circuit_type: bool = True) -> bool Add RLC gap boundary on component and replace it with a circuit port. The circuit port supports only 2-pin components. :Parameters: **component** : :class:`python:str` Reference designator of the RLC component. **circuit_type** : :ref:`bool ` When ``True`` circuit type are defined, if ``False`` gap type will be used instead (compatible with HFSS 3D modeler). Default value is ``True``. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. !! processed by numpydoc !! .. py:method:: create_coax_port(padstackinstance: Union[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, int], use_dot_separator: bool = True, name: Optional[str] = None, create_on_top: bool = True) -> Optional[str] Create HFSS 3Dlayout coaxial lumped port on a pastack Requires to have solder ball defined before calling this method. :Parameters: **padstackinstance** : `Edb.Cell.Primitive.PadstackInstance` or :class:`python:int` Padstack instance object. **use_dot_separator** : :ref:`bool `, :obj:`optional` Whether to use ``.`` as the separator for the naming convention, which is ``[component][net][pin]``. The default is ``True``. If ``False``, ``_`` is used as the separator instead. **name** : :class:`python:str` Port name for overwriting the default port-naming convention, which is ``[component][net][pin]``. The port name must be unique. If a port with the specified name already exists, the default naming convention is used so that port creation does not fail. :Returns: :class:`python:str` Terminal name. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin = edb.padstacks.instances[0] >>> edb.source_excitation.create_coax_port(pin, name="CoaxPort1") .. !! processed by numpydoc !! .. py:method:: create_circuit_port_on_pin(pos_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], neg_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], impedance: Union[int, float] = 50, port_name: Optional[str] = None) -> Optional[str] Create a circuit port on a pin. :Parameters: **pos_pin** : :obj:`Object` Edb Pin **neg_pin** : :obj:`Object` Edb Pin **impedance** : :class:`python:float` Port Impedance **port_name** : :class:`python:str`, :obj:`optional` Port Name :Returns: :class:`python:str` Port Name. .. rubric:: Examples >>> from pyedb import Edb >>> edbapp = Edb("myaedbfolder", "project name", "release version") >>> pins = edbapp.components.get_pin_from_component("U2A5") >>> edbapp.siwave.create_circuit_port_on_pin(pins[0], pins[1], 50, "port_name") .. !! processed by numpydoc !! .. py:method:: create_voltage_source_on_pin(pos_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], neg_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], voltage_value: Union[int, float] = 0, phase_value: Union[int, float] = 0, source_name: Optional[str] = None) -> Optional[str] Create a voltage source. :Parameters: **pos_pin** : :obj:`Object` Positive Pin. **neg_pin** : :obj:`Object` Negative Pin. **voltage_value** : :class:`python:float`, :obj:`optional` Value for the voltage. The default is ``3.3``. **phase_value** : :obj:`optional` Value for the phase. The default is ``0``. **source_name** : :class:`python:str`, :obj:`optional` Name of the source. The default is ``""``. :Returns: :class:`python:str` Source Name. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin1 = edb.components["U1"].pins["VCC"] >>> pin2 = edb.components["U1"].pins["GND"] >>> edb.source_excitation.create_voltage_source_on_pin(pin1, pin2, 3.3, name="VSource1") .. !! processed by numpydoc !! .. py:method:: create_current_source_on_pin(pos_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], neg_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], current_value: Union[int, float] = 0, phase_value: Union[int, float] = 0, source_name: Optional[str] = None) -> Optional[str] Create a voltage source. :Parameters: **pos_pin** : :obj:`Object` Positive Pin. **neg_pin** : :obj:`Object` Negative Pin. **voltage_value** : :class:`python:float`, :obj:`optional` Value for the voltage. The default is ``3.3``. **phase_value** : :obj:`optional` Value for the phase. The default is ``0``. **source_name** : :class:`python:str`, :obj:`optional` Name of the source. The default is ``""``. :Returns: :class:`python:str` Source Name. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin1 = edb.components["U1"].pins["IN"] >>> pin2 = edb.components["U1"].pins["GND"] >>> edb.source_excitation.create_current_source_on_pin(pin1, pin2, 0.1, name="ISource1") .. !! processed by numpydoc !! .. py:method:: create_resistor_on_pin(pos_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], neg_pin: Union[str, pyedb.grpc.database.primitive.padstack_instance.PadstackInstance], rvalue: Union[int, float] = 1, resistor_name: Optional[str] = '') -> Optional[str] Create a Resistor boundary between two given pins.. :Parameters: **pos_pin** : :obj:`Object` Positive Pin. **neg_pin** : :obj:`Object` Negative Pin. **rvalue** : :class:`python:float`, :obj:`optional` Resistance value. The default is ``1``. **resistor_name** : :class:`python:str`, :obj:`optional` Name of the resistor. The default is ``""``. :Returns: :class:`python:str` Name of the resistor. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin1 = edb.components["U1"].pins["R1_p"] >>> pin2 = edb.components["U1"].pins["R1_n"] >>> edb.source_excitation.create_resistor_on_pin(pin1, pin2, 50, "R1") .. !! processed by numpydoc !! .. py:method:: create_circuit_port_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: str, negative_net_name: Optional[str] = None, impedance_value: Union[int, float] = 50, port_name: Optional[str] = None) -> Optional[str] Create a circuit port on a NET. It groups all pins belonging to the specified net and then applies the port on PinGroups. :Parameters: **positive_component_name** : :class:`python:str` Name of the positive component. **positive_net_name** : :class:`python:str` Name of the positive net. **negative_component_name** : :class:`python:str`, :obj:`optional` Name of the negative component. The default is ``None``, in which case the name of the positive net is assigned. **negative_net_name** : :class:`python:str`, :obj:`optional` Name of the negative net name. The default is ``None`` which will look for GND Nets. **impedance_value** : :class:`python:float`, :obj:`optional` Port impedance value. The default is ``50``. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``""``. :Returns: :class:`python:str` The name of the port. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_circuit_port_on_net("U1", "VCC", "U1", "GND", 50, "PowerPort") .. !! processed by numpydoc !! .. py:method:: create_pin_group_terminal(positive_pins: Union[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, List[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance]], negatives_pins: Optional[Union[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, List[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance]]] = None, name: Optional[str] = None, impedance: Union[int, float, str] = 50, source_type: str = 'circuit_port', magnitude: Union[float, str] = 1.0, phase: Union[float, str] = 0, r: float = 0.0, l: float = 0.0, c: float = 0.0) -> Optional[str] Create a pin group terminal. :Parameters: **positive_pins** : :obj:`positive` :obj:`pins` used. :class: `PadstackInstance` or List[:class: ´PadstackInstance´] **negatives_pins** : :obj:`negative` :obj:`pins` used. :class: `PadstackInstance` or List[:class: ´PadstackInstance´] **impedance** : :class:`python:float`, :class:`python:int` or :class:`python:str` Terminal impedance. Default value is `50` Ohms. **source_type** : :class:`python:str` Source type assigned on terminal. Supported values : `"circuit_port"`, `"lumped_port"`, `"current_source"`, `"voltage_source"`, `"rlc"`, `"dc_terminal"`. Default value is `"circuit_port"`. **name** : :class:`python:str`, :obj:`optional` Source name. **magnitude** : :class:`python:float`, :class:`python:int` or :class:`python:str`, :obj:`optional` source magnitude. **phase** : :class:`python:float`, :class:`python:int` or :class:`python:str`, :obj:`optional` phase magnitude. **r** : :class:`python:float`, :obj:`optional` Resistor value. **l** : :class:`python:float`, :obj:`optional` Inductor value. **c** : :class:`python:float`, :obj:`optional` Capacitor value. .. !! processed by numpydoc !! .. py:method:: create_voltage_source_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: Optional[str] = None, negative_net_name: Optional[str] = None, voltage_value: Union[int, float] = 0, phase_value: Union[int, float] = 0, source_name: Optional[str] = None) -> Optional[str] Create a voltage source. :Parameters: **positive_component_name** : :class:`python:str` Name of the positive component. **positive_net_name** : :class:`python:str` Name of the positive net. **negative_component_name** : :class:`python:str`, :obj:`optional` Name of the negative component. The default is ``None``, in which case the name of the positive net is assigned. **negative_net_name** : :class:`python:str`, :obj:`optional` Name of the negative net name. The default is ``None`` which will look for GND Nets. **voltage_value** : :class:`python:float`, :obj:`optional` Value for the voltage. The default is ``3.3``. **phase_value** : :obj:`optional` Value for the phase. The default is ``0``. **source_name** : :class:`python:str`, :obj:`optional` Name of the source. The default is ``""``. :Returns: :class:`python:str` The name of the source. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_voltage_source_on_net("U1", "VCC", "U1", "GND", 3.3, name="VCC_Source") .. !! processed by numpydoc !! .. py:method:: create_current_source_on_net(positive_component_name: str, positive_net_name: str, negative_component_name: Optional[str] = None, negative_net_name: Optional[str] = None, current_value: Union[int, float] = 0, phase_value: Union[int, float] = 0, source_name: Optional[str] = None) -> Optional[str] Create a voltage source. :Parameters: **positive_component_name** : :class:`python:str` Name of the positive component. **positive_net_name** : :class:`python:str` Name of the positive net. **negative_component_name** : :class:`python:str`, :obj:`optional` Name of the negative component. The default is ``None``, in which case the name of the positive net is assigned. **negative_net_name** : :class:`python:str`, :obj:`optional` Name of the negative net name. The default is ``None`` which will look for GND Nets. **voltage_value** : :class:`python:float`, :obj:`optional` Value for the voltage. The default is ``3.3``. **phase_value** : :obj:`optional` Value for the phase. The default is ``0``. **source_name** : :class:`python:str`, :obj:`optional` Name of the source. The default is ``""``. :Returns: :class:`python:str` The name of the source. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_current_source_on_net("U1", "INPUT", "U1", "GND", 0.1, name="InputCurrent") "InputCurrent" .. !! processed by numpydoc !! .. py:method:: create_coax_port_on_component(ref_des_list: Union[str, List[str]], net_list: Union[str, List[str]], delete_existing_terminal: bool = False) -> List[str] Create a coaxial port on a component or component list on a net or net list. The name of the new coaxial port is automatically assigned. :Parameters: **ref_des_list** : :class:`python:list`, :class:`python:str` List of one or more reference designators. **net_list** : :class:`python:list`, :class:`python:str` List of one or more nets. **delete_existing_terminal** : :ref:`bool ` Delete existing terminal with same name if exists. Port naming convention is `ref_des`_`pin.net.name`_`pin.name` :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_coax_port_on_component(["U1"], ["RF1", "RF2"]) .. !! processed by numpydoc !! .. py:method:: check_before_terminal_assignement(connectable: Any, delete_existing_terminal: bool = False) -> bool .. py:method:: create_differential_wave_port(positive_primitive_id: Union[int, pyedb.grpc.database.primitive.primitive.Primitive], positive_points_on_edge: List[float], negative_primitive_id: Union[int, pyedb.grpc.database.primitive.primitive.Primitive], negative_points_on_edge: List[float], port_name: Optional[str] = None, horizontal_extent_factor: Union[int, float] = 5, vertical_extent_factor: Union[int, float] = 3, pec_launch_width: str = '0.01mm') -> Tuple[str, pyedb.grpc.database.terminal.bundle_terminal.BundleTerminal] Create a differential wave port. :Parameters: **positive_primitive_id** : :class:`python:int`, :obj:`EDBPrimitives` Primitive ID of the positive terminal. **positive_points_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge. **negative_primitive_id** : :class:`python:int`, :obj:`EDBPrimitives` Primitive ID of the negative terminal. **negative_points_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. **horizontal_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Horizontal extent factor. The default value is ``5``. **vertical_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Vertical extent factor. The default value is ``3``. **pec_launch_width** : :class:`python:str`, :obj:`optional` Launch Width of PEC. The default value is ``"0.01mm"``. :Returns: :class:`python:tuple` The tuple contains: (port_name, pyedb.dotnet.database.edb_data.sources.ExcitationDifferential). .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> port_name, port = edb.source_excitation.create_differential_wave_port(0, [0, 0], 1, [0, 0.2]) .. !! processed by numpydoc !! .. py:method:: create_wave_port(prim_id: Union[int, pyedb.grpc.database.primitive.primitive.Primitive], point_on_edge: List[float], port_name: Optional[str] = None, impedance: Union[int, float] = 50, horizontal_extent_factor: Union[int, float] = 5, vertical_extent_factor: Union[int, float] = 3, pec_launch_width: str = '0.01mm') -> Tuple[str, pyedb.grpc.database.ports.ports.WavePort] Create a wave port. :Parameters: **prim_id** : :class:`python:int`, :obj:`Primitive` Primitive ID. **point_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. **impedance** : :class:`python:int`, :class:`python:float`, :obj:`optional` Impedance of the port. The default value is ``50``. **horizontal_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Horizontal extent factor. The default value is ``5``. **vertical_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Vertical extent factor. The default value is ``3``. **pec_launch_width** : :class:`python:str`, :obj:`optional` Launch Width of PEC. The default value is ``"0.01mm"``. :Returns: :class:`python:tuple` The tuple contains: (Port name, pyedb.dotnet.database.edb_data.sources.Excitation). .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> port_name, port = edb.source_excitation.create_wave_port(0, [0, 0]) .. !! processed by numpydoc !! .. py:method:: create_edge_port_vertical(prim_id: int, point_on_edge: List[float], port_name: Optional[str] = None, impedance: Union[int, float] = 50, reference_layer: Optional[str] = None, hfss_type: str = 'Gap', horizontal_extent_factor: Union[int, float] = 5, vertical_extent_factor: Union[int, float] = 3, pec_launch_width: str = '0.01mm') -> str Create a vertical edge port. :Parameters: **prim_id** : :class:`python:int` Primitive ID. **point_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. **impedance** : :class:`python:int`, :class:`python:float`, :obj:`optional` Impedance of the port. The default value is ``50``. **reference_layer** : :class:`python:str`, :obj:`optional` Reference layer of the port. The default is ``None``. **hfss_type** : :class:`python:str`, :obj:`optional` Type of the port. The default value is ``"Gap"``. Options are ``"Gap"``, ``"Wave"``. **horizontal_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Horizontal extent factor. The default value is ``5``. **vertical_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Vertical extent factor. The default value is ``3``. **radial_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Radial extent factor. The default value is ``0``. **pec_launch_width** : :class:`python:str`, :obj:`optional` Launch Width of PEC. The default value is ``"0.01mm"``. :Returns: :class:`python:str` Port name. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> term = edb.source_excitation.create_edge_port_vertical(0, [0, 0], reference_layer="TopLayer") .. !! processed by numpydoc !! .. py:method:: create_edge_port_horizontal(prim_id: Union[int, pyedb.grpc.database.primitive.primitive.Primitive], point_on_edge: List[float], ref_prim_id: Optional[Union[int, pyedb.grpc.database.primitive.primitive.Primitive]] = None, point_on_ref_edge: Optional[List[float]] = None, port_name: Optional[str] = None, impedance: Union[int, float] = 50, layer_alignment: str = 'Upper') -> Optional[pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal] Create a horizontal edge port. :Parameters: **prim_id** : :class:`python:int` Primitive ID. **point_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be on the target edge but not on the two ends of the edge. **ref_prim_id** : :class:`python:int`, :obj:`optional` Reference primitive ID. The default is ``None``. **point_on_ref_edge** : :class:`python:list`, :obj:`optional` Coordinate of the point to define the reference edge terminal. The point must be on the target edge but not on the two ends of the edge. The default is ``None``. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. **impedance** : :class:`python:int`, :class:`python:float`, :obj:`optional` Impedance of the port. The default value is ``50``. **layer_alignment** : :class:`python:str`, :obj:`optional` Layer alignment. The default value is ``Upper``. Options are ``"Upper"``, ``"Lower"``. :Returns: :class:`python:str` Name of the port. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_edge_port_horizontal(0, [0, 0], 1, [0, 0.1], "EdgePort") .. !! processed by numpydoc !! .. py:method:: create_lumped_port_on_net(nets: Optional[Union[str, List[str]]] = None, reference_layer: Optional[Union[str, pyedb.grpc.database.layers.stackup_layer.StackupLayer]] = None, return_points_only: bool = False, digit_resolution: int = 6, at_bounding_box: bool = True) -> bool Create an edge port on nets. This command looks for traces and polygons on the nets and tries to assign vertical lumped port. :Parameters: **nets** : :class:`python:list`, :obj:`optional` List of nets, str or Edb net. **reference_layer** : :class:`python:str`, :obj:`Edb` layer. Name or Edb layer object. **return_points_only** : :ref:`bool `, :obj:`optional` Use this boolean when you want to return only the points from the edges and not creating ports. Default value is ``False``. **digit_resolution** : :class:`python:int`, :obj:`optional` The number of digits carried for the edge location accuracy. The default value is ``6``. **at_bounding_box** : :ref:`bool ` When ``True`` will keep the edges from traces at the layout bounding box location. This is recommended when a cutout has been performed before and lumped ports have to be created on ending traces. Default value is ``True``. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> points = edb.source_excitation.create_lumped_port_on_net(["Net1"], return_points_only=True) .. !! processed by numpydoc !! .. py:method:: create_vertical_circuit_port_on_clipped_traces(nets: Optional[Union[str, List[str], pyedb.grpc.database.net.net.Net, List[pyedb.grpc.database.net.net.Net]]] = None, reference_net: Optional[Union[str, pyedb.grpc.database.net.net.Net]] = None, user_defined_extent: Optional[Union[List[float], ansys.edb.core.geometry.polygon_data.PolygonData]] = None) -> Union[List[List[str]], bool] Create an edge port on clipped signal traces. :Parameters: **nets** : :class:`python:list`, :obj:`optional` String of one net or EDB net or a list of multiple nets or EDB nets. **reference_net** : :class:`python:str`, :obj:`Edb` net. Name or EDB reference net. **user_defined_extent** : [:obj:`x`, :obj:`y`], :obj:`EDB` :obj:`PolygonData` Use this point list or PolygonData object to check if ports are at this polygon border. :Returns: [[:class:`python:str`]] Nested list of str, with net name as first value, X value for point at border, Y value for point at border, and terminal name. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> terminals = edb.source_excitation.create_vertical_circuit_port_on_clipped_traces(["Net1"], "GND") .. !! processed by numpydoc !! .. py:method:: create_bundle_wave_port(primitives_id: List[Union[int, pyedb.grpc.database.primitive.primitive.Primitive]], points_on_edge: List[List[float]], port_name: Optional[str] = None, horizontal_extent_factor: Union[int, float] = 5, vertical_extent_factor: Union[int, float] = 3, pec_launch_width: str = '0.01mm') -> Tuple[str, pyedb.grpc.database.ports.ports.BundleWavePort] Create a bundle wave port. :Parameters: **primitives_id** : :class:`python:list` Primitive ID of the positive terminal. **points_on_edge** : :class:`python:list` Coordinate of the point to define the edge terminal. The point must be close to the target edge but not on the two ends of the edge. **port_name** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. **horizontal_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Horizontal extent factor. The default value is ``5``. **vertical_extent_factor** : :class:`python:int`, :class:`python:float`, :obj:`optional` Vertical extent factor. The default value is ``3``. **pec_launch_width** : :class:`python:str`, :obj:`optional` Launch Width of PEC. The default value is ``"0.01mm"``. :Returns: :class:`python:tuple` The tuple contains: (port_name, pyedb.egacy.database.edb_data.sources.ExcitationDifferential). .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> port_name, port = edb.source_excitation.create_bundle_wave_port([0, 1], [[0, 0], [0, 0.2]]) .. !! processed by numpydoc !! .. py:method:: create_hfss_ports_on_padstack(pinpos: pyedb.grpc.database.primitive.padstack_instance.PadstackInstance, portname: Optional[str] = None) -> bool Create an HFSS port on a padstack. :Parameters: **pinpos** Position of the pin. **portname** : :class:`python:str`, :obj:`optional` Name of the port. The default is ``None``. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin = edb.padstacks.instances[0] >>> edb.source_excitation.create_hfss_ports_on_padstack(pin, "Port1") .. !! processed by numpydoc !! .. py:method:: get_ports_number() -> int Return the total number of excitation ports in a layout. :Parameters: **None** .. :Returns: :class:`python:int` Number of ports. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> num_ports = edb.source_excitation.get_ports_number() .. !! processed by numpydoc !! .. py:method:: get_point_terminal(name: str, net_name: str, location: List[float], layer: str) -> pyedb.grpc.database.terminal.point_terminal.PointTerminal Place terminal between two points. :Parameters: **name** : str, Name of the terminal. **net_name** : :class:`python:str` Name of the net. **location** : :class:`python:list` Location of the terminal. **layer** : str, Layer of the terminal. :Returns: :class:`PointTerminal ` .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> term = edb.source_excitation.get_point_terminal("Term1", "Net1", [0, 0], "TopLayer") .. !! processed by numpydoc !! .. py:method:: create_rlc_boundary_on_pins(positive_pin: Optional[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance] = None, negative_pin: Optional[pyedb.grpc.database.primitive.padstack_instance.PadstackInstance] = None, rvalue: float = 0.0, lvalue: float = 0.0, cvalue: float = 0.0) -> Union[pyedb.grpc.database.terminal.terminal.Terminal, bool] Create hfss rlc boundary on pins. :Parameters: **positive_pin** : :obj:`Positive` pin. Edb.Cell.Primitive.PadstackInstance **negative_pin** : :obj:`Negative` pin. Edb.Cell.Primitive.PadstackInstance **rvalue** : :obj:`Resistance` :obj:`value` .. **lvalue** : :obj:`Inductance` :obj:`value` .. **cvalue . Capacitance value.** .. :Returns: :ref:`bool ` ``True`` when successful, ``False`` when failed. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> pin1 = edb.components["U1"].pins["Pin1"] >>> pin2 = edb.components["U1"].pins["Pin2"] >>> term = edb.source_excitation.create_rlc_boundary_on_pins(pin1, pin2, rvalue=50) .. !! processed by numpydoc !! .. py:method:: create_edge_port_on_polygon(polygon: Optional[pyedb.grpc.database.primitive.primitive.Primitive] = None, reference_polygon: Optional[pyedb.grpc.database.primitive.primitive.Primitive] = None, terminal_point: Optional[List[float]] = None, reference_point: Optional[List[float]] = None, reference_layer: Optional[Union[str, pyedb.grpc.database.layers.stackup_layer.StackupLayer]] = None, port_name: Optional[str] = None, port_impedance: Union[int, float] = 50.0, force_circuit_port: bool = False) -> Optional[str] Create lumped port between two edges from two different polygons. Can also create a vertical port when the reference layer name is only provided. When a port is created between two edge from two polygons which don't belong to the same layer, a circuit port will be automatically created instead of lumped. To enforce the circuit port instead of lumped,use the boolean force_circuit_port. :Parameters: **polygon** : :obj:`The` :obj:`EDB` :obj:`polygon` :obj:`object` :obj:`used` :obj:`to` :obj:`assign` :obj:`the` port. Edb.Cell.Primitive.Polygon object. **reference_polygon** : :obj:`The` :obj:`EDB` :obj:`polygon` :obj:`object` :obj:`used` :obj:`to` :obj:`define` :obj:`the` :obj:`port` reference. Edb.Cell.Primitive.Polygon object. **terminal_point** : :obj:`The` :obj:`coordinate` :obj:`of` :obj:`the` :obj:`point` :obj:`to` :obj:`define` :obj:`the` :obj:`edge` :obj:`terminal` :obj:`of` :obj:`the` port. :obj:`This` :obj:`point` :obj:`must` :obj:`be` .. **located on the edge of the polygon where the port has to be placed. For instance taking the middle point** .. **of an edge is a good practice but any point of the edge should be valid. Taking a corner might cause unwanted** .. **port location.** list[float, float] with values provided in meter. **reference_point** : :obj:`same` :obj:`as` :obj:`terminal_point` :obj:`but` :obj:`used` :obj:`for` :obj:`defining` :obj:`the` :obj:`reference` :obj:`location` :obj:`on` :obj:`the` edge. list[float, float] with values provided in meter. **reference_layer** : :obj:`Name` :obj:`used` :obj:`to` :obj:`define` :obj:`port` :obj:`reference` :obj:`for` :obj:`vertical` ports. str the layer name. **port_name** : :obj:`Name` :obj:`of` :obj:`the` port. str. **port_impedance** : :obj:`port` :obj:`impedance` value. :obj:`Default` :obj:`value` :obj:`is` 50 Ohms. float, impedance value. **force_circuit_port ; used to force circuit port creation instead of lumped. Works for vertical and coplanar** .. **ports.** .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> poly = edb.modeler.primitives[0] >>> ref_poly = edb.modeler.primitives[1] >>> edb.source_excitation.create_edge_port_on_polygon(poly, ref_poly, [0, 0], [0.1, 0]) .. !! processed by numpydoc !! .. py:method:: create_port_between_pin_and_layer(component_name: Optional[str] = None, pins_name: Optional[Union[str, List[str]]] = None, layer_name: Optional[str] = None, reference_net: Optional[str] = None, impedance: Union[int, float] = 50.0) -> bool Create circuit port between pin and a reference layer. :Parameters: **component_name** : :class:`python:str` Component name. The default is ``None``. **pins_name** : :class:`python:str` Pin name or list of pin names. The default is ``None``. **layer_name** : :class:`python:str` Layer name. The default is ``None``. **reference_net** : :class:`python:str` Reference net name. The default is ``None``. **impedance** : :class:`python:float`, :obj:`optional` Port impedance. The default is ``50.0`` in ohms. :Returns: :obj:`PadstackInstanceTerminal` Created terminal. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> terms = edb.source_excitation.create_port_between_pin_and_layer("U1", "Pin1", "GND", "GND") .. !! processed by numpydoc !! .. py:method:: create_current_source(terminal: Union[pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal, pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal], ref_terminal: Union[pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal, pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal]) -> bool Create a current source. :Parameters: **terminal** : :class:`EdgeTerminal `:obj:`or` :class:`PadstackInstanceTerminal ` or :class:`PointTerminal ` or :class:`PinGroupTerminal `. Positive terminal of the source. **ref_terminal** : :class:`EdgeTerminal ` :obj:`or` :class:`pyedb.grpc.database.terminals.PadstackInstanceTerminal` or :class:`PadstackInstanceTerminal ` or :class:`PinGroupTerminal `. Negative terminal of the source. :Returns: :class:`ExcitationSources ` .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_current_source_on_pin_group("PG1", "PG2", 0.1, name="ISource1") .. !! processed by numpydoc !! .. py:method:: create_current_source_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, magnitude: Union[int, float] = 1, phase: Union[int, float] = 0, name: Optional[str] = None) -> bool Create current source between two pin groups. :Parameters: **pos_pin_group_name** : :class:`python:str` Name of the positive pin group. **neg_pin_group_name** : :class:`python:str` Name of the negative pin group. **magnitude** : :class:`python:int`, :class:`python:float`, :obj:`optional` Magnitude of the source. **phase** : :class:`python:int`, :class:`python:float`, :obj:`optional` Phase of the source :Returns: :ref:`bool ` .. .. !! processed by numpydoc !! .. py:method:: create_voltage_source(terminal: Union[pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal, pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal], ref_terminal: Union[pyedb.grpc.database.terminal.padstack_instance_terminal.PadstackInstanceTerminal, pyedb.grpc.database.terminal.edge_terminal.EdgeTerminal], magnitude: Union[int, float] = 1, phase: Union[int, float] = 0) -> bool Create a voltage source. :Parameters: **name** : :class:`python:str`, :obj:`optional` Voltage source name **terminal** : :class:`EdgeTerminal `, :class:`PadstackInstanceTerminal `, :class:`PointTerminal `, :class:`PinGroupTerminal `, Positive terminal of the source. **ref_terminal** : :class:`EdgeTerminal `, :class:`pyedb.grpc.database.terminals.PadstackInstanceTerminal`, :class:`PadstackInstanceTerminal `, :class:`PinGroupTerminal `, Negative terminal of the source. **magnitude** : :class:`python:int`, :class:`python:float`, :obj:`optional` Magnitude of the source. **phase** : :class:`python:int`, :class:`python:float`, :obj:`optional` Phase of the source :Returns: class:`ExcitationSources ` .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_voltage_source_on_pin_group("PG1", "PG2", 3.3, name="VSource1") .. !! processed by numpydoc !! .. py:method:: create_voltage_source_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, magnitude: Union[int, float] = 1, phase: Union[int, float] = 0, name: Optional[str] = None, impedance: Union[int, float] = 0.001) -> bool Create voltage source between two pin groups. :Parameters: **pos_pin_group_name** : :class:`python:str` Name of the positive pin group. **neg_pin_group_name** : :class:`python:str` Name of the negative pin group. **magnitude** : :class:`python:int`, :class:`python:float`, :obj:`optional` Magnitude of the source. **phase** : :class:`python:int`, :class:`python:float`, :obj:`optional` Phase of the source :Returns: :ref:`bool ` .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_voltage_probe_on_pin_group("Probe1", "PG1", "PG2") .. !! processed by numpydoc !! .. py:method:: create_voltage_probe(terminal: pyedb.grpc.database.terminal.terminal.Terminal, ref_terminal: pyedb.grpc.database.terminal.terminal.Terminal) -> pyedb.grpc.database.terminal.terminal.Terminal Create a voltage probe. :Parameters: **terminal** : :class:`EdgeTerminal `, :class:`PadstackInstanceTerminal `, :class:`PointTerminal `, :class:`PinGroupTerminal `, Positive terminal of the port. **ref_terminal** : :class:`EdgeTerminal `, :class:`pyedb.grpc.database.terminals.PadstackInstanceTerminal`, :class:`PadstackInstanceTerminal `, :class:`PinGroupTerminal `, Negative terminal of the probe. :Returns: :class:`Terminal ` .. .. !! processed by numpydoc !! .. py:method:: create_voltage_probe_on_pin_group(probe_name: str, pos_pin_group_name: str, neg_pin_group_name: str, impedance: Union[int, float] = 1000000) -> bool Create voltage probe between two pin groups. :Parameters: **probe_name** : :class:`python:str` Name of the probe. **pos_pin_group_name** : :class:`python:str` Name of the positive pin group. **neg_pin_group_name** : :class:`python:str` Name of the negative pin group. **impedance** : :class:`python:int`, :class:`python:float`, :obj:`optional` Phase of the source. :Returns: :ref:`bool ` .. .. !! processed by numpydoc !! .. py:method:: create_dc_terminal(component_name: str, net_name: str, source_name: Optional[str] = None) -> Optional[str] Create a dc terminal. :Parameters: **component_name** : :class:`python:str` Name of the positive component. **net_name** : :class:`python:str` Name of the positive net. **source_name** : :class:`python:str`, :obj:`optional` Name of the source. The default is ``""``. :Returns: :class:`python:str` The name of the source. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_dc_terminal("U1", "VCC", "DC_VCC") .. !! processed by numpydoc !! .. py:method:: create_circuit_port_on_pin_group(pos_pin_group_name: str, neg_pin_group_name: str, impedance: Union[int, float] = 50, name: Optional[str] = None) -> bool Create a port between two pin groups. :Parameters: **pos_pin_group_name** : :class:`python:str` Name of the positive pin group. **neg_pin_group_name** : :class:`python:str` Name of the negative pin group. **impedance** : :class:`python:int`, :class:`python:float`, :obj:`optional` Impedance of the port. Default is ``50``. **name** : :class:`python:str`, :obj:`optional` Port name. :Returns: :ref:`bool ` .. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> edb.source_excitation.create_circuit_port_on_pin_group("PG1", "PG2", 50, "Port1") .. !! processed by numpydoc !! .. py:method:: place_voltage_probe(name: str, positive_net_name: str, positive_location: List[float], positive_layer: str, negative_net_name: str, negative_location: List[float], negative_layer: str) -> pyedb.grpc.database.terminal.terminal.Terminal Place a voltage probe between two points. :Parameters: **name** : str, Name of the probe. **positive_net_name** : :class:`python:str` Name of the positive net. **positive_location** : :class:`python:list` Location of the positive terminal. **positive_layer** : str, Layer of the positive terminal. **negative_net_name** : str, Name of the negative net. **negative_location** : :class:`python:list` Location of the negative terminal. **negative_layer** : :class:`python:str` Layer of the negative terminal. .. rubric:: Examples >>> from pyedb import Edb >>> edb = Edb() >>> probe = edb.source_excitation.place_voltage_probe( ... "Probe1", "Net1", [0, 0], "TopLayer", "GND", [0.1, 0], "TopLayer" ... ) .. !! processed by numpydoc !!