Set up EDB for PCB DC IR Analysis#
This example shows how to set up the electronics database (EDB) for DC IR analysis from a single configuration file.
Import the required packages#
[1]:
import json
import os
import tempfile
from ansys.aedt.core import Hfss3dLayout, Icepak
from ansys.aedt.core.downloads import download_file
from pyedb import Edb
AEDT_VERSION = "2024.2"
NG_MODE = False
Download the example PCB data.
[2]:
temp_folder = tempfile.TemporaryDirectory(suffix=".ansys")
file_edb = download_file(source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name)
Load example layout#
[3]:
edbapp = Edb(file_edb, edbversion=AEDT_VERSION)
PyAEDT INFO: Logger is initialized in EDB.
PyAEDT INFO: legacy v0.34.3
PyAEDT INFO: Python version 3.10.11 (tags/v3.10.11:7d4cc5a, Apr 5 2023, 00:38:17) [MSC v.1929 64 bit (AMD64)]
PyAEDT INFO: Database ANSYS-HSD_V1.aedb Opened in 2024.2
PyAEDT INFO: Cell main Opened
PyAEDT INFO: Builder was initialized.
PyAEDT INFO: EDB initialized.
Create an empty dictionary to host all configurations#
[4]:
cfg = dict()
cfg["sources"] = []
Update stackup#
[5]:
cfg["stackup"] = {
"layers": [
{"name": "Top", "type": "signal", "material": "copper", "fill_material": "FR4_epoxy", "thickness": "0.035mm"},
{"name": "DE1", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.1mm"},
{
"name": "Inner1",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{"name": "DE2", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.088mm"},
{
"name": "Inner2",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{"name": "DE3", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.1mm"},
{
"name": "Inner3",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{
"name": "FR4_epoxy-1mm",
"type": "dielectric",
"material": "FR4_epoxy",
"fill_material": "",
"thickness": "1mm",
},
{
"name": "Inner4",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{"name": "DE5", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.1mm"},
{
"name": "Inner5",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{"name": "DE6", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.088mm"},
{
"name": "Inner6",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.017mm",
},
{"name": "DE7", "type": "dielectric", "material": "FR4_epoxy", "fill_material": "", "thickness": "0.1mm"},
{
"name": "Bottom",
"type": "signal",
"material": "copper",
"fill_material": "FR4_epoxy",
"thickness": "0.035mm",
},
]
}
Define voltage source#
[6]:
cfg["sources"].append(
{
"name": "vrm",
"reference_designator": "U2",
"type": "voltage",
"magnitude": 1,
"positive_terminal": {"net": "1V0"},
"negative_terminal": {"net": "GND"},
}
)
Define current source#
[7]:
cfg["sources"].append(
{
"name": "U1_1V0",
"reference_designator": "U1",
"type": "current",
"magnitude": 10,
"positive_terminal": {"net": "1V0"},
"negative_terminal": {"net": "GND"},
}
)
Define SIwave DC IR analysis setup#
[8]:
cfg["setups"] = [
{
"name": "siwave_1",
"type": "siwave_dc",
"dc_slider_position": 1,
"dc_ir_settings": {"export_dc_thermal_data": True},
}
]
Define Cutout#
[9]:
cfg["operations"] = {
"cutout": {"signal_list": ["1V0"], "reference_list": ["GND"], "extent_type": "ConvexHull", "expansion_size": "20mm"}
}
Define package for thermal analysis (optional)#
[10]:
cfg["package_definitions"] = [
{
"name": "package_1",
"component_definition": "ALTR-FBGA1517-Ansys",
"maximum_power": 0.5,
"therm_cond": 2,
"theta_jb": 3,
"theta_jc": 4,
"height": "1mm",
"apply_to_all": False,
"components": ["U1"],
},
]
Write configuration into a JSON file#
[11]:
file_json = os.path.join(temp_folder.name, "edb_configuration.json")
with open(file_json, "w") as f:
json.dump(cfg, f, indent=4, ensure_ascii=False)
Import configuration into example layout#
[12]:
edbapp.configuration.load(config_file=file_json)
[12]:
<pyedb.configuration.cfg_data.CfgData at 0x15956e2c3a0>
Apply configuration to EDB.
[13]:
edbapp.configuration.run()
PyAEDT INFO: Cutout Multithread started.
PyAEDT INFO: Net clean up Elapsed time: 0m 2sec
PyAEDT INFO: Extent Creation Elapsed time: 0m 0sec
PyAEDT INFO: 533 Padstack Instances deleted. Elapsed time: 0m 1sec
PyAEDT INFO: 105 Primitives deleted. Elapsed time: 0m 2sec
PyAEDT INFO: 470 components deleted
PyAEDT INFO: Cutout completed. Elapsed time: 0m 5sec
[13]:
True
Save and close EDB.
[14]:
edbapp.save()
edbapp.close()
[14]:
True
The configured EDB file is saved in a temp folder.
[15]:
print(temp_folder.name)
C:\Users\ansys\AppData\Local\Temp\tmpn4n2a1fr.ansys
Load edb into HFSS 3D Layout.#
[16]:
h3d = Hfss3dLayout(edbapp.edbpath, version=AEDT_VERSION, non_graphical=NG_MODE, new_desktop=True)
PyAEDT INFO: Python version 3.10.11 (tags/v3.10.11:7d4cc5a, Apr 5 2023, 00:38:17) [MSC v.1929 64 bit (AMD64)]
PyAEDT INFO: PyAEDT version 0.12.dev0.
PyAEDT INFO: Initializing new Desktop session.
PyAEDT INFO: Log on console is enabled.
PyAEDT INFO: Log on file C:\Users\ansys\AppData\Local\Temp\pyaedt_ansys_d5742601-d182-492e-96df-ea175aac3029.log is enabled.
PyAEDT INFO: Log on AEDT is enabled.
PyAEDT INFO: Debug logger is disabled. PyAEDT methods will not be logged.
PyAEDT INFO: Launching PyAEDT with gRPC plugin.
PyAEDT INFO: New AEDT session is starting on gRPC port 59993
PyAEDT INFO: AEDT installation Path C:\Program Files\AnsysEM\v242\Win64
PyAEDT INFO: Ansoft.ElectronicsDesktop.2024.2 version started with process ID 4076.
PyAEDT INFO: EDB folder C:\Users\ansys\AppData\Local\Temp\tmpn4n2a1fr.ansys\edb/ANSYS-HSD_V1.aedb has been imported to project ANSYS-HSD_V1
PyAEDT INFO: Active Design set to 0;main
PyAEDT INFO: Aedt Objects correctly read
Prepare for electro-thermal analysis in Icepak (Optional)#
[17]:
h3d.modeler.set_temperature_dependence(include_temperature_dependence=True, enable_feedback=True, ambient_temp=22)
PyAEDT INFO: Loading Modeler.
PyAEDT INFO: Modeler loaded.
PyAEDT INFO: EDB loaded.
PyAEDT INFO: Layers loaded.
PyAEDT INFO: Primitives loaded.
PyAEDT INFO: Modeler class has been initialized! Elapsed time: 0m 0sec
PyAEDT INFO: Set the temperature dependence for the design.
PyAEDT INFO: Assigned Objects Temperature
[17]:
True
Analyze#
[18]:
h3d.analyze()
PyAEDT INFO: Key Desktop/ActiveDSOConfigurations/HFSS 3D Layout Design correctly changed.
PyAEDT INFO: Solving all design setups.
PyAEDT INFO: Key Desktop/ActiveDSOConfigurations/HFSS 3D Layout Design correctly changed.
PyAEDT INFO: Design setup None solved correctly in 0.0h 0.0m 37.0s
[18]:
True
Plot DC voltage#
[19]:
voltage = h3d.post.create_fieldplot_layers_nets(
layers_nets=[
["Inner2", "1V0"],
],
quantity="Voltage",
setup="siwave_1",
)
PyAEDT INFO: Parsing C:/Users/ansys/AppData/Local/Temp/tmpn4n2a1fr.ansys/edb/ANSYS-HSD_V1.aedt.
PyAEDT INFO: File C:/Users/ansys/AppData/Local/Temp/tmpn4n2a1fr.ansys/edb/ANSYS-HSD_V1.aedt correctly loaded. Elapsed time: 0m 0sec
PyAEDT INFO: aedt file load time 0.016663789749145508
PyAEDT INFO: PostProcessor class has been initialized! Elapsed time: 0m 0sec
PyAEDT INFO: Post class has been initialized! Elapsed time: 0m 0sec
PyAEDT INFO: Logger is initialized in EDB.
PyAEDT INFO: legacy v0.34.3
PyAEDT INFO: Python version 3.10.11 (tags/v3.10.11:7d4cc5a, Apr 5 2023, 00:38:17) [MSC v.1929 64 bit (AMD64)]
PyAEDT INFO: Database ANSYS-HSD_V1.aedb Opened in 2024.2
PyAEDT INFO: Cell main Opened
PyAEDT INFO: Builder was initialized.
PyAEDT INFO: EDB initialized.
[20]:
file_path_image = os.path.join(temp_folder.name, "voltage.jpg")
voltage.export_image(
full_path=file_path_image,
width=640,
height=480,
orientation="isometric",
display_wireframe=True,
selections=None,
show_region=True,
show_axis=True,
show_grid=True,
show_ruler=True,
)
[20]:
'C:\\Users\\ansys\\AppData\\Local\\Temp\\tmpn4n2a1fr.ansys\\voltage.jpg'
Plot power density#
[21]:
power_density = h3d.post.create_fieldplot_layers_nets(
layers_nets=[
["Inner2", "no-net"],
],
quantity="Power Density",
setup="siwave_1",
)
[22]:
file_path_image = os.path.join(temp_folder.name, "power_density.jpg")
power_density.export_image(
full_path=file_path_image,
width=640,
height=480,
orientation="isometric",
display_wireframe=True,
selections=None,
show_region=True,
show_axis=True,
show_grid=True,
show_ruler=True,
)
[22]:
'C:\\Users\\ansys\\AppData\\Local\\Temp\\tmpn4n2a1fr.ansys\\power_density.jpg'
Compute power loss#
[23]:
p_layers = h3d.post.compute_power_by_layer(layers=["Top"])
print(p_layers)
{'Top': '8.6897195056157076e-03'}
[24]:
p_nets = h3d.post.compute_power_by_nets(nets=["1V0"])
print(p_nets)
{'Bottom': '1.0954008692844821e+00'}
Save HFSS 3D Layout project#
[25]:
h3d.save_project()
PyAEDT INFO: Project ANSYS-HSD_V1 Saved correctly
[25]:
True
Create an Icepak design#
[26]:
ipk = Icepak(version=AEDT_VERSION, non_graphical=NG_MODE, new_desktop=False)
PyAEDT INFO: Python version 3.10.11 (tags/v3.10.11:7d4cc5a, Apr 5 2023, 00:38:17) [MSC v.1929 64 bit (AMD64)]
PyAEDT INFO: PyAEDT version 0.12.dev0.
PyAEDT INFO: Returning found Desktop session with PID 4076!
PyAEDT INFO: No project is defined. Project ANSYS-HSD_V1 exists and has been read.
PyAEDT INFO: No consistent unique design is present. Inserting a new design.
PyAEDT INFO: Added design 'Icepak_VQN' of type Icepak.
PyAEDT INFO: Aedt Objects correctly read
PyAEDT INFO: Parsing C:/Users/ansys/AppData/Local/Temp/tmpn4n2a1fr.ansys/edb/ANSYS-HSD_V1.aedt.
PyAEDT INFO: File C:/Users/ansys/AppData/Local/Temp/tmpn4n2a1fr.ansys/edb/ANSYS-HSD_V1.aedt correctly loaded. Elapsed time: 0m 0sec
PyAEDT INFO: aedt file load time 0.03242945671081543
Create PCB#
[27]:
pcb = ipk.create_ipk_3dcomponent_pcb(
compName="PCB_pyAEDT",
setupLinkInfo=[h3d.project_file, h3d.design_name, "siwave_1", True, True],
solutionFreq=None,
resolution=0,
extent_type="Bounding Box",
powerin="0",
)
PyAEDT INFO: Modeler class has been initialized! Elapsed time: 0m 0sec
PyAEDT INFO: Materials class has been initialized! Elapsed time: 0m 0sec
Include pckage definition from Edb#
[28]:
pcb.included_parts = "Device"
Adjust air region#
[29]:
region = ipk.modeler["Region"]
faces = [f.id for f in region.faces]
ipk.assign_pressure_free_opening(assignment=faces, boundary_name="Outlet")
[29]:
<ansys.aedt.core.modules.boundary.BoundaryObject at 0x1592be98f70>
Setup mesh#
[30]:
glob_msh = ipk.mesh.global_mesh_region
glob_msh.global_region.positive_z_padding_type = "Absolute Offset"
glob_msh.global_region.positive_z_padding = "50 mm"
glob_msh.global_region.negative_z_padding_type = "Absolute Offset"
glob_msh.global_region.negative_z_padding = "80 mm"
PyAEDT WARNING: No mesh operation found.
PyAEDT WARNING: No mesh region found.
PyAEDT INFO: Parsing design objects. This operation can take time
PyAEDT INFO: 3D Modeler objects parsed. Elapsed time: 0m 0sec
PyAEDT INFO: Mesh class has been initialized! Elapsed time: 0m 0sec
[31]:
glob_msh = ipk.mesh.global_mesh_region
glob_msh.manual_settings = True
glob_msh.settings["EnableMLM"] = True
glob_msh.settings["EnforeMLMType"] = "2D"
glob_msh.settings["2DMLMType"] = "Auto"
glob_msh.settings["MaxElementSizeY"] = "2mm"
glob_msh.settings["MaxElementSizeX"] = "2mm"
glob_msh.settings["MaxElementSizeZ"] = "3mm"
glob_msh.settings["MaxLevels"] = "2"
[32]:
glob_msh.update()
[32]:
True
Place monitor#
[33]:
cpu = ipk.modeler["PCB_pyAEDT_U1_device"]
m1 = ipk.monitor.assign_face_monitor(
face_id=cpu.top_face_z.id,
monitor_quantity="Temperature",
monitor_name="TemperatureMonitor1",
)
Create Icepak setup#
[34]:
setup1 = ipk.create_setup(MaxIterations=10)
PyAEDT INFO: Key MaxIterations matched internal key 'Convergence Criteria - Max Iterations' with confidence of 52.
Add 2-way coupling to the setup
[35]:
ipk.assign_2way_coupling(number_of_iterations=1)
[35]:
True
Save#
[36]:
ipk.save_project()
PyAEDT INFO: Project ANSYS-HSD_V1 Saved correctly
[36]:
True
Shut Down Electronics Desktop#
[37]:
ipk.release_desktop()
PyAEDT INFO: Desktop has been released and closed.
[37]:
True
All project files are saved in the folder temp_file.dir. If you’ve run this example as a Jupyter notebook you can retrieve those project files.