EDB: SYZ analysis

This example shows how you can use PyAEDT to set up SYZ analysis on Serdes channel. The input is the name of the differential nets. The positive net is PCIe_Gen4_TX3_CAP_P. The negative net is PCIe_Gen4_TX3_CAP_N. The code will place ports on driver and receiver components.

Perform required imports

Perform required imports, which includes importing a section.

import time

from pyaedt import Hfss3dLayout

import pyedb
from pyedb.generic.general_methods import generate_unique_folder_name
from pyedb.misc.downloads import download_file

Download file

Download the AEDB file and copy it in the temporary folder.

temp_folder = generate_unique_folder_name()
targetfile = download_file("edb/ANSYS-HSD_V1.aedb", destination=temp_folder)
time.sleep(5)

print(targetfile)

C:\Users\ansys\AppData\Local\Temp\pyedb_prj_HQS\edb/ANSYS-HSD_V1.aedb

Configure EDB

Launch the pyedb.Edb class, using EDB 2023 R2.

edbapp = pyedb.Edb(edbpath=targetfile, edbversion="2024.1")

Generate extended nets

An extended net is a connection between two nets that are usually connected through a passive component like a resistor or capacitor.

edbapp.extended_nets.auto_identify_signal(resistor_below=10, inductor_below=1, capacitor_above=1e-9)

[['SFPA_Tx_Fault'], ['SFPA_Tx_Disable'], ['SFPA_SDA'], ['SFPA_SCL'], ['SFPA_Rx_LOS'], ['SFPA_RS1'], ['SFPA_RS0'], ['SFPA__Mod_ABS'], ['PCIe_Gen4_TX3_CAP_P', 'PCIe_Gen4_TX3_P'], ['PCIe_Gen4_TX3_CAP_N', 'PCIe_Gen4_TX3_N'], ['PCIe_Gen4_TX2_CAP_P', 'PCIe_Gen4_TX2_P'], ['PCIe_Gen4_TX2_CAP_N', 'PCIe_Gen4_TX2_N'], ['PCIe_Gen4_TX1_CAP_P', 'PCIe_Gen4_TX1_P'], ['PCIe_Gen4_TX1_CAP_N', 'PCIe_Gen4_TX1_N'], ['PCIe_Gen4_TX0_CAP_P', 'PCIe_Gen4_TX0_P'], ['PCIe_Gen4_TX0_CAP_N', 'PCIe_Gen4_TX0_N'], ['PCIe_Gen4_RX3_P'], ['PCIe_Gen4_RX3_N'], ['USB3_SSRX_C_P', 'USB3_SSTX_P'], ['USB3_SSRX_C_N', 'USB3_SSTX_N'], ['NetR1_2'], ['NetIC2_5'], ['NetD3_2', 'AVCC_1V3', 'GND', '5V', 'PDEN', 'USB3_VBUS', 'SFPA_VCCR', 'SFPA_VCCT', 'NetIC1_8', 'NetC34_2', 'NetC34_1', 'NetC271_1', '2V5', 'VDD_DDR', 'NetR22_1', '+VREFDDR4', '1V0', 'NetR8_1', 'NetR119_2', 'GND_DP', 'NetJ1_14', 'NetJ1_13', 'NetJ1_19', 'NetC291_2', '1.8V_DVDDH', '1.2V_DVDDL', '3.3V_AVDDH', '1.2V_AVDDL', '1.2V_AVDLL_PLL', 'NetC180_2', 'NetC179_2', 'NetC178_2', 'NetC177_2', 'DP_3V3', '12V-In', 'NetC43_2', 'NetC42_2', 'NetC25_2', 'NetC18_2', 'NetC9_2'], ['NetC50_2', 'NetC50_1'], ['NetR117_2'], ['NetR116_2'], ['NetR66_1'], ['NetR65_1'], ['NetR34_2'], ['NetC35_1'], ['NetC33_2'], ['NetR124_1'], ['NetR123_1'], ['NetR122_2'], ['NetR121_2'], ['NetR120_2'], ['NetR116_1'], ['NetR114_2'], ['NetR104_1'], ['NetR102_1'], ['NetR100_2'], ['NetR99_1'], ['NetR26_1'], ['NetR25_1'], ['NetR24_2'], ['NetR13_1'], ['NetR12_1'], ['NetR11_2'], ['NetIC1_9'], ['NetIC1_7'], ['NetC26_2'], ['NetC26_1'], ['NetC19_2', 'NetC19_1'], ['NetC10_2', 'NetC10_1'], ['DDR4_ALERT3'], ['DDR4_ALERT2'], ['A10_GNDSENSE'], ['PCIe_Gen4_WAKE_L'], ['PCIe_Gen4_W_DISABLE_L'], ['PCIe_Gen4_USB_D_P'], ['PCIe_Gen4_USB_D_N'], ['PCIe_Gen4_SMB_DATA'], ['PCIe_Gen4_SMB_CLK'], ['PCIe_Gen4_RX2_P'], ['PCIe_Gen4_RX2_N'], ['PCIe_Gen4_RX1_P'], ['PCIe_Gen4_RX1_N'], ['PCIe_Gen4_RX0_P'], ['PCIe_Gen4_RX0_N'], ['PCIe_Gen4_RST_L'], ['PCIe_Gen4_REFCLK_P'], ['PCIe_Gen4_REFCLK_N'], ['PCIe_Gen4_CLKREQ_L'], ['NetU13_2'], ['NetU13_1'], ['NetU9_46'], ['NetSW1_4'], ['NetSW1_3'], ['NetSW1_2'], ['NetR115_2'], ['NetR108_2'], ['NetR105_2'], ['NetR82_1'], ['NetJ3_2'], ['NetJ2_17'], ['NetJ2_16'], ['NetJ2_14'], ['NetJ2_13'], ['NetJ1_18'], ['LVDS_CH12_P'], ['LVDS_CH12_N'], ['LVDS_CH11_P'], ['LVDS_CH11_N'], ['LVDS_CH10_P'], ['LVDS_CH10_N'], ['LVDS_CH09_P'], ['LVDS_CH09_N'], ['LVDS_CH08_P'], ['LVDS_CH08_N'], ['LVDS_CH07_P'], ['LVDS_CH07_N'], ['LVDS_CH06_P'], ['LVDS_CH06_N'], ['LVDS_CH05_P'], ['LVDS_CH05_N'], ['LVDS_CH04_P'], ['LVDS_CH04_N'], ['LVDS_CH03_P'], ['LVDS_CH03_N'], ['LVDS_CH02_P'], ['LVDS_CH02_N'], ['LVDS_CH01_P'], ['LVDS_CH01_N'], ['DDR4_DQS5_P'], ['DDR4_DQS5_N'], ['DDR4_DQS4_P'], ['DDR4_DQS4_N'], ['DDR4_DQS7_P'], ['DDR4_DQS7_N'], ['DDR4_DQS6_P'], ['DDR4_DQS6_N'], ['DDR4_DQ47'], ['DDR4_DQ46'], ['DDR4_DQ45'], ['DDR4_DQ44'], ['DDR4_DQ43'], ['DDR4_DQ42'], ['DDR4_DQ41'], ['DDR4_DQ40'], ['DDR4_DQ39'], ['DDR4_DQ38'], ['DDR4_DQ37'], ['DDR4_DQ36'], ['DDR4_DQ35'], ['DDR4_DQ34'], ['DDR4_DQ33'], ['DDR4_DQ32'], ['DDR4_DQ63'], ['DDR4_DQ62'], ['DDR4_DQ61'], ['DDR4_DQ60'], ['DDR4_DQ59'], ['DDR4_DQ58'], ['DDR4_DQ57'], ['DDR4_DQ56'], ['DDR4_DQ55'], ['DDR4_DQ54'], ['DDR4_DQ53'], ['DDR4_DQ52'], ['DDR4_DQ51'], ['DDR4_DQ50'], ['DDR4_DQ49'], ['DDR4_DQ48'], ['DDR4_DM5'], ['DDR4_DM4'], ['DDR4_DM7'], ['DDR4_DM6'], ['ENET_HPS_TXD3'], ['ENET_HPS_TXD2'], ['ENET_HPS_TXD1'], ['ENET_HPS_TXD0'], ['ENET_HPS_RXD0'], ['JTAG_TRST'], ['JTAG_TMS'], ['JTAG_TDO'], ['JTAG_TDI'], ['JTAG_TCK'], ['DDR4_DQS3_P'], ['DDR4_DQS3_N'], ['DDR4_DQS2_P'], ['DDR4_DQS2_N'], ['DDR4_DQS1_P'], ['DDR4_DQS1_N'], ['DDR4_DQS0_P'], ['DDR4_DQS0_N'], ['DDR4_CLK_P'], ['DDR4_CLK_N'], ['SFPA_TX_P'], ['SFPA_TX_N'], ['SFPA_RX_P'], ['SFPA_RX_N'], ['REFCLK_DP_P'], ['REFCLK_DP_N'], ['REFCLK0_FMCB_P'], ['REFCLK0_FMCB_N'], ['PLL_1V8'], ['NetU1_AW13'], ['NetU1_AW11'], ['NetU1_AV11'], ['NetU1_AP13'], ['NetR83_1'], ['NetR113_2'], ['NetR106_1'], ['USB3_SSRX_P'], ['USB3_SSRX_N'], ['USB3_D_P'], ['USB3_D_N'], ['TRD4_N'], ['TRD4_P'], ['TRD3_N'], ['TRD3_P'], ['TRD2_N'], ['TRD2_P'], ['TRD1_N'], ['TRD1_P'], ['ENET_HPS_TX_EN'], ['ENET_HPS_RXD3'], ['ENET_HPS_RXD2'], ['ENET_HPS_RXD1'], ['ENET_HPS_RX_DV'], ['ENET_HPS_RX_CLK'], ['ENET_HPS_MDIO'], ['ENET_HPS_MDC'], ['ENET_HPS_GTX_CLK'], ['DP_ML_LANE3_P', 'DP_ML_LANE3_C_P'], ['DP_ML_LANE2_P', 'DP_ML_LANE2_C_P'], ['DP_ML_LANE1_P', 'DP_ML_LANE1_C_P'], ['DP_ML_LANE0_P', 'DP_ML_LANE0_C_P'], ['DP_ML_LANE3_N', 'DP_ML_LANE3_C_N'], ['DP_ML_LANE2_N', 'DP_ML_LANE2_C_N'], ['DP_ML_LANE1_N', 'DP_ML_LANE1_C_N'], ['DP_ML_LANE0_N', 'DP_ML_LANE0_C_N'], ['DDR4_WEN'], ['DDR4_RESETN'], ['DDR4_RAS'], ['DDR4_PAR'], ['DDR4_ODT'], ['DDR4_DQ31'], ['DDR4_DQ30'], ['DDR4_DQ29'], ['DDR4_DQ28'], ['DDR4_DQ27'], ['DDR4_DQ26'], ['DDR4_DQ25'], ['DDR4_DQ24'], ['DDR4_DQ23'], ['DDR4_DQ22'], ['DDR4_DQ21'], ['DDR4_DQ20'], ['DDR4_DQ19'], ['DDR4_DQ18'], ['DDR4_DQ17'], ['DDR4_DQ16'], ['DDR4_DQ15'], ['DDR4_DQ14'], ['DDR4_DQ13'], ['DDR4_DQ12'], ['DDR4_DQ11'], ['DDR4_DQ10'], ['DDR4_DQ9'], ['DDR4_DQ8'], ['DDR4_DQ7'], ['DDR4_DQ6'], ['DDR4_DQ5'], ['DDR4_DQ4'], ['DDR4_DQ3'], ['DDR4_DQ2'], ['DDR4_DQ1'], ['DDR4_DQ0'], ['DDR4_DM3'], ['DDR4_DM2'], ['DDR4_DM1'], ['DDR4_DM0'], ['DDR4_CSN'], ['DDR4_CKE'], ['DDR4_CAS'], ['DDR4_BG0'], ['DDR4_BA1'], ['DDR4_BA0'], ['DDR4_ALERT1'], ['DDR4_ALERT0'], ['DDR4_A13'], ['DDR4_A12'], ['DDR4_A11'], ['DDR4_A10'], ['DDR4_A9'], ['DDR4_A8'], ['DDR4_A7'], ['DDR4_A6'], ['DDR4_ACT'], ['DDR4_A4'], ['DDR4_A3'], ['DDR4_A2'], ['DDR4_A1'], ['DDR4_A0'], ['CLOCK_I2C_SDA'], ['CLOCK_I2C_SCL'], ['DDR4_A5']]

Review extended net properties

Review extended net properties.

diff_p = edbapp.nets["PCIe_Gen4_TX3_CAP_P"]
diff_n = edbapp.nets["PCIe_Gen4_TX3_CAP_N"]

nets_p = list(diff_p.extended_net.nets.keys())
nets_n = list(diff_n.extended_net.nets.keys())

comp_p = list(diff_p.extended_net.components.keys())
comp_n = list(diff_n.extended_net.components.keys())

rlc_p = list(diff_p.extended_net.rlc.keys())
rlc_n = list(diff_n.extended_net.rlc.keys())

print(comp_p, rlc_p, comp_n, rlc_n, sep="\n")

['U1', 'C379', 'X1']
['C379']
['U1', 'C380', 'X1']
['C380']

Prepare input data for port creation

Prepare input data for port creation.

ports = []
for net_name, net_obj in diff_p.extended_net.nets.items():
    for comp_name, comp_obj in net_obj.components.items():
        if comp_obj.type not in ["Resistor", "Capacitor", "Inductor"]:
            ports.append(
                {"port_name": "{}_{}".format(comp_name, net_name), "comp_name": comp_name, "net_name": net_name}
            )

for net_name, net_obj in diff_n.extended_net.nets.items():
    for comp_name, comp_obj in net_obj.components.items():
        if comp_obj.type not in ["Resistor", "Capacitor", "Inductor"]:
            ports.append(
                {"port_name": "{}_{}".format(comp_name, net_name), "comp_name": comp_name, "net_name": net_name}
            )

print(*ports, sep="\n")

{'port_name': 'U1_PCIe_Gen4_TX3_CAP_P', 'comp_name': 'U1', 'net_name': 'PCIe_Gen4_TX3_CAP_P'}
{'port_name': 'X1_PCIe_Gen4_TX3_P', 'comp_name': 'X1', 'net_name': 'PCIe_Gen4_TX3_P'}
{'port_name': 'U1_PCIe_Gen4_TX3_CAP_N', 'comp_name': 'U1', 'net_name': 'PCIe_Gen4_TX3_CAP_N'}
{'port_name': 'X1_PCIe_Gen4_TX3_N', 'comp_name': 'X1', 'net_name': 'PCIe_Gen4_TX3_N'}

Create ports

Solder balls are generated automatically. The default port type is coax port.

for d in ports:
    port_name = d["port_name"]
    comp_name = d["comp_name"]
    net_name = d["net_name"]
    edbapp.components.create_port_on_component(component=comp_name, net_list=net_name, port_name=port_name)

Cutout

Delete all irrelevant nets.

nets = []
nets.extend(nets_p)
nets.extend(nets_n)

edbapp.cutout(signal_list=nets, reference_list=["GND"], extent_type="Bounding")

[[0.016139999279999998, 0.05419999847], [0.016139999279999998, 0.03255000329], [0.06875000112, 0.03255000329], [0.06875000112, 0.05419999847]]

Create SYZ analysis setup

Create SIwave SYZ setup.

setup = edbapp.create_siwave_syz_setup("setup1")
setup.add_frequency_sweep(
    frequency_sweep=[
        ["linear count", "0", "1kHz", 1],
        ["log scale", "1kHz", "0.1GHz", 10],
        ["linear scale", "0.1GHz", "10GHz", "0.1GHz"],
    ]
)

<pyedb.dotnet.edb_core.utilities.simulation_setup.EdbFrequencySweep object at 0x000001AA4CB474C0>

Save and close AEDT

Close AEDT.

edbapp.save()
edbapp.close_edb()

True

Launch Hfss3dLayout

To do SYZ analysis, you must launch HFSS 3D Layout and import EDB into it.

h3d = Hfss3dLayout(targetfile, specified_version="2024.1", new_desktop_session=True)

Set differential pair

Set differential pair.

h3d.set_differential_pair(
    positive_terminal="U1_PCIe_Gen4_TX3_CAP_P", negative_terminal="U1_PCIe_Gen4_TX3_CAP_N", diff_name="PAIR_U1"
)
h3d.set_differential_pair(
    positive_terminal="X1_PCIe_Gen4_TX3_P", negative_terminal="X1_PCIe_Gen4_TX3_N", diff_name="PAIR_X1"
)

True

Solve and plot results

Solve and plot the results.

h3d.analyze(num_cores=4)

True

Create report outside AEDT

Create a report.

h3d.post.create_report("dB(S(PAIR_U1,PAIR_U1))", context="Differential Pairs")

<pyaedt.modules.report_templates.Standard object at 0x000001AA4CB453F0>

Close AEDT

Close AEDT.

h3d.save_project()
print("Project is saved to {}".format(h3d.project_path))
h3d.release_desktop(True, True)

Project is saved to C:/Users/ansys/AppData/Local/Temp/pyedb_prj_HQS/edb/

True